Conductor via and dielectric via

[Cyrina]

Hi all !
i'm confused about the difference between conductor layer and dielectric layer on ADS? the dielectric layer is it filled by materiel or not? could anyone help me please

 

[dick_freebird]

Dielectric layers insulate the metal layers from each
other and from the silicon (or III-V material). Vias
are cut and filled in the dielectric layers (field ox,
ILD1, ILD2, ...) to create a conductive connection
between adjacent metal levels or semiconductor and
Met1 (here specifically, it would be called contact).

Most foundries will show you cutaways which make
this more clear than text would. Also Google Images
will have plenty.

There have been occasionally in the RFIC space,
flows with "air bridge" dielectric features (to make
interlayer capacitance as low as can be, physics)
but this is abnormal (as a silicon guy). So "filled
or not" is "usually filled, check the recipe".

 

[timof]

Are you asking about conductor/dielectric stack in IC (integrated circuit) or in PCB (printed circuit board)?
The details are different between these two, regarding via construction.

 

[Cyrina]

Are you asking about conductor/dielectric stack in IC (integrated circuit) or in PCB (printed circuit board)?
The details are different between these two, regarding via construction.

Im asking about the nature of vias (conductor or dielectric), im importing a structure build in ADS into HFWorks to simulate it, i want to know if i will apply material to vias parts or just apply PEC(perfect electric conductor) as boundary condition

 

[erikl]

Im asking about the nature of vias (conductor or dielectric), im importing a structure build in ADS into HFWorks to simulate it, i want to know if i will apply material to vias parts or just apply PEC(perfect electric conductor) as boundary condition

Vias are connections between metal layers and so obviously have to be conductive. Depending on the process they will be filled with Al or Cu - but also combinations with other metals are possible, e.g. Ti, Ta, Mo, V ...

 

[timof]

Im asking about the nature of vias (conductor or dielectric), im importing a structure build in ADS into HFWorks to simulate it, i want to know if i will apply material to vias parts or just apply PEC(perfect electric conductor) as boundary condition

If you include metal/conductor layers below and above the via into simulation - you cannot define a boundary condition at via.
Current and voltage drop on via is not known and will be established through a self-consistent solution.

If, on the other hand, via leads to "outside" (for example, via on the topmost metal layer included into simulation) - sometimes, you can define a boundary condition on it (voltage or current - and possibly with some series resistance).
If via dimensions are large (as compared to a characteristic scale of voltage or current non-uniformity) - you would need to discretize it.
If via is small in size and current non-uniformity inside it is not important - it can be treated as a vertical resistor, without discretization.
Most simulators, though, are not providing such an option - to switch (automatically or not) between the dimensionality representation of metals and vias.

Normally, vias are conductors, not dielectrics.

 

[volker@muehlhaus]

Normally, vias are conductors, not dielectrics.

That's the normal case.

For special modelling cases (a dielectric insert in a dielectric layer) with the FEM solver, ADS also supports a "dielectric via". If you create your own ADS substrate file reader, you might want to include that feature.