Maximum phase margin and stability

[Alpacca]

Hello!

I was wondering - is it possible to obtain a phase margin over 180 degrees? Get positive phase at 0 dB gain? I'm designing LDO and I can't find the right value of output capacitor to get any phase margin.

Thanks in advance for explanation!

 

[frankrose]

Point of compensation is to place dominant pole and 2nd lowest frequency pole far from each other. Reachable max. phase margin is 90° then.
If you want to compensate at the LDO's output it can be bad. Increase the capacitance at the dominant pole of the circuit, it is not always at the output.
But if you want to make the output to the dominant pole, you should use a huge capacitor at the output and try to decrease the present dominant pole's capacitance. It is hard, if the dominant pole's resistive part is huge as usually it is.

 

[Alpacca]

What can I do if I have such characteristic? There's big drop from -90 to -270 degrees and output capacitor does nothing. The only solution is to modify dominant poles?

 

[FvM]

Which quantity is shown in the bode plot? Doesn't look like the useful loop gain of a LDO or similar feedback system, e.g. because the gain is dropping at low frequencies.

Please clarify with reference to the circuit and measurement setup.

 

[Alpacca]

That is the circuit:


I measure AC characteristic at the node between RF1 and RF2, that's the result:

 

[FvM]

Thanks for the clarification. There are issues of different kind:

- It's no correct loop gain measurement setup. The range below 1 kHz is distorted by the source AC coupling. Use a better considered setup to measure loop over the full frequency range. Use Middlebrook's method.

- The BSS84 output transistor creates a RHP zero (all-pass) by its large gate-drain capacitance which causes the non minimum-phase characteristic. Need to shift the RHP zero right of the unity gain frequency.

- - - Updated - - -

Here's a correct loop gain analysis. RHP zero still in effect.

 

[Alpacca]

Can I move this RHP zero by adjusting capacitance at output? I can't see this zero - I see poles (-90 degrees of phase characteristic), but I can't see this zero, there's no +90 degrees phase shift...

 

[FvM]

I can't see this zero - I see poles (-90 degrees of phase characteristic), but I can't see this zero, there's no +90 degrees phase shift...

Wrong expectation, RHP zero involves negative phase shift.

 

[frankrose]

RHP zero means Right Half Plane Zero. It is not Left Half Plane Zero, which can shift +90°. RHPZ shifts the phase in the opposite direction, like a pole, but it can increase magnitude as a zero on the left half plane of a pole-zero plot.
You cannot adjust it with pole capacitances, the Cds of your MOS creates it. The RHPZ frequency is gm/Cds, so if you want to shift it to higher frequency increase the current of your MOS device. And you can still decrease your dominant pole's frequency. Both of them will help on stability.

 

[Alpacca]

Can you show me on phase characteristic this RHP zero? I put in parallel more and more transistors to increase gm, but characteristic doesn't change.
In fact, I have no idea what I am doing, all phase characteristics that I've seen start from zero and here I have +180 degrees at the beginning. Phase margin is result of comparement with -180 degrees, it's impossible to get it in this circuit.

 

[FvM]

Critical parameter is the ratio of Cgd to gm, adding more transistors can't reduce it. Instead increase I'd as suggested.

 

[frankrose]

Sorry, I wanted to say Cgd, as FvM. Not the Cds cause RHPZ, the Cgd is the reason. Still, increase the current rather to increase gm, because if you add more paralel devices you just increase the parasitic capacitances.

 

[Alpacca]

Is there any other method than changing the RF1 and RF2 resistors?

 

[frankrose]

Yeah, those are too high related to the MOSFET's parasitic capacitances. But you can increase the I1 current too if you don't want to change the resistors.

 

[Alpacca]

Since it's inverting circuit (at 0 Hz we have 180 degrees phase), phase at 0 dB can't reach 0 degrees. So in this situation phase margin is determined at 0 degrees., am I correct?

 

[frankrose]

Since it's inverting circuit (at 0 Hz we have 180 degrees phase)...

Yes.

...phase at 0 dB can't reach 0 degrees...

No, it will if there are a pole and an RHPZ before 0dB's frequency.

For example if the 2nd pole's frequency is equals with the RHPZ frequency they together don't modify the magnitude's curve but they can shift the phase with -180°. The 1st pole shifts the phase with -90°, so the total phase shift can be -270°. 180° is the initial phase shift at DC, thus 180°+(-270°)=-90°. Thus the phase can be any value between +90° and -90° at 0dB, and it depends on where is the 2nd pole and the RHPZ.

So in this situation phase margin is determined at 0 degrees., am I correct?

Phase Margin is the phase shift at 0dB magnitude in your case.