VHDL code for phase matching

[ananthan95]

vhdl code for phase matching two sine waves from a transmitter and a receiver? anyone pls!
the receiver wave is out of phase with the transmitter wave

 

[ThisIsNotSam]

Re: vhdl code for phase matching

more info needed... how are these said sine waves encoded? surely they are not analog signals

 

[rca]

detecting when the wave cross zero?
Two pointers are found, then do the difference.

 

[ananthan95]

Re: vhdl code for phase matching

TX_DATA 32767,40609,47995,54496,59735,63406,65296,63406,59735,54496,47995,40609,32767,24924,17538,11037,5798,2129,238,2129,5798,11037,17538,24924);
RX_DATA : (54496,59735,63406,65296,63406,59735,54496,47995,40609,32767,24924,17538,11037,5798,2129,238,2129,5798,11037,17538,24924,32767,40609,47995);

see these are the data points. if u observe, they ar the same set of points but RX_DATA starts little late (to make a phase difference).
i want to detect when rxdata crosses zero so that i can phase atch it with the txdata

 

[ThisIsNotSam]

If they are the same, use any data point as reference and look for the same data point in the other stream. Count cycles and you will know the difference. Delay the wave by X many cycles and you will put them in sync, if that is what you want.

 

[FvM]

Choosing sine input, exactly one period, same magnitude values is a rather special case.

Real signal example can expose level differences, offset, noise, phase shift not equal to an integer multiply of sampling period. Also varying and possibly unknown signal period must be considered for the general case.

Modern digital oscilloscopes measure phase e.g. by detecting zero crossing, derive signal period and zero crossing time shift and hence phase difference. High pass filtering (to cancel offsets) and noise suppression (e.g. by introducing hysteresis for the z.c. detector) is usually applied. Signal interpolation can increase the phase resolution.

 

[ananthan95]

okay.. that is helpful. I kind of figured out a method to phase match these data points. but let me explain my idea. these are the outputs from an Analog to Digital Converter connected to a Data Acquisition System. so these values are continously supplied to the fpga. i already have a refference wave in fpga. there is a phase difference between the refference and incoming wave. that is what i am trying to correct. if you have any ideas regarding the issue please share.

 

[KlausST]

Hi,

Insteadofusing an FPGA internal sinewave...
I'd generate two digital signal with 90° phase shift but with the frequency of the internal sine. (Should be simple)

Then use these two signals for two controlled rectifiers. (Multiply the input signal with +1 / -1 according digital signal.)
The input signal of the controlled rectifier is your input from the ADC.
The outputs of the rectifier need to be low pass filtered.

The quotient of both filtered outputs gives the phase shift.

Maybe you can optimize the function and use only one rectifier...and check for the zero cross of the filtered output.

Filter: implementing a 2nd order filter isn't difficult. Either use a classical (low tap count) IIR topology or use a biquad topology.

Klaus

 

[FvM]

I'm yet missing a specification of operation range, e.g. frequency, magnitude, signal-to-noise ratio, accuracy requirements. We are solving similar problems for different purposes, e.g. signal analysis, inverter control, each solution has different requirements and uses respectively different methods.

 

[ananthan95]

okay. the sampling rate is 24 data points per cycle. from the ADC, the data is continuously fed into the FPGA. the data I have given above are just examples. let's say i don't have any control over the received or transmitted data. a wave is transmitted out from fpga to an analog circuit via a DAC and the same wave is coming back through a ADC. eventhough they are same waves since there is an offset voltage issue in the analog system, the phase of the incoming wave s altered. now i have to nullify the phase difference between the 2 waves and find out the amplitude change happened due to the offset voltage. this is my original problem.
so i used a set of 24 data points (which I created using MATLAB. if these points are plotted, a sine wave will be obtained) and i just made a phase difference by changing the order of the data points. so the above points are just example took from a random sine wave. i just needed some datas to start with

 

[filip.amator]

In the general case calculating the cross-correlation function for different delays will give you an answer what is exact time shift between two signals: a reference one and acquired by ADC converter. There is a convenient approach by using Wiener–Khinchin
theorem involving FFT calculation any you can get for free IP cores to calculate it.

 

[KlausST]

Hi,

24 data points per cycle

I´ve never seen an ADC given it´s sampling rate with such a unit: "points per cycle".

Klaus

 

[ananthan95]

okay..so i found out its scheme demodulation that I am trying to achieve here

 

[ananthan95]

oops sorry.. it is synchronous demodulation

 

[ananthan95]

during synchronous demodulation, is it enough to phase match the signal only once at the beginning? or is it necessary to look for phase mismatch during the reception process?

 

[filip.amator]

If your signal is modulated with the same frequency as your reference frequency then you have to only adjust phase.

 

[ananthan95]

yea ok. so you think implementing such a code in VHDL is possible? because I have a bunch of integer data to process with.

 

[FvM]

I fear that the problem is still poorly specified. Synchronous demodulation e.g. uses quite often a PLL for carrier recovery. But different modulation types imply different carrier recovery methods.