tayyab786
Junior Member level 3
i create 1d array in verilog code like this
now in always blocks i am comparing some input logic like this
the line "cts_1= {3'b000,channel[1]};" give latches
now question is how to remove latches. and why this line create latches
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 reg[7:0] channel[1:length-3]; integer i ; initial begin for (i = 1 ; i <= length-3 ; i = i+1) begin channel[i] = i * 10; end end
now in always blocks i am comparing some input logic like this
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 always@ (posedge clk or posedge rst ) begin if (rst) begin cts_1 = 11'bz ; cts_2 = 11'bz ; cts_3 = 11'bz ; cts_4 = 11'bz ; cts_5 = 11'bz ; cts_6 = 11'bz ; cts_7 = 11'bz ; cts_8 = 11'bz ; count = 1 ; count1 = 0 ; end else begin if( user[1:3] == 3'b000 && count1[0]!=1 ) //Count1---only one time access only begin cts_1= {3'b000,channel[count]}; count=count+1; count1[0]=1; end else begin cts_1 = cts_1; end
the line "cts_1= {3'b000,channel[1]};" give latches
now question is how to remove latches. and why this line create latches
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