use rising edge and falling edge of the clock in vhdl

[matin-kh]

hi every one,
I want to use both edge of the clock but I have problem to develop it.
I write a simple code for the process like below to check it:

---

Code VHDL - [expand]
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process(x(3),res)
    begin
    if(res='1') then
        a<='0';
        b<='0';
    elsif (x(3)'event and x(3)='1') then
            a<='1';
            b<='0';
    elsif (x(3)'event and x(3)='0') then
            a<='0';
            b<='1';
    end if;
end process;

---

it has error, so I changed it to:

---

Code VHDL - [expand]
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process(x(3),res)
    begin
    if(res='1') then
        a<='0';
        b<='0';
    elsif (x(3)'event) then
                if(x(3)='1')then
            a<='1';
            b<='0';
            elsif (x(3)='0') then
            a<='0';
            b<='1';
                end if;
    end if;
end process;

---

i have error in that code too! I write like below:

---

Code VHDL - [expand]
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process(x(3),res)
    begin
    if(res='1') then
        a<='0';
        b<='0';
    elsif (x(3)'event and x(3)='1') then
        a<='1';
        b<='0';
    end if;
end process;
process(x(3),res)
    begin
    if(res='1') then
        a<='0';
        b<='0';
    elsif (x(3)'event and x(3)='0') then
        a<='0';
        b<='1';
    end if;
end process;

---

I have error in thatcode too!
just a process with an edge is without any error. so what should I do?
Regards
Matin

 

[vGoodtimes]

FPGAs have very few DDR registers. They are only used for IO pins.

FPGAs have clock synthesizers (PLLs and similar) that can generate the desired 2x rate clock signals. This makes internal DDR registers and emulation of DDR registers less important in FPGA designs. It is easier to just generate the normal clock signal of 2x frequency than to deal with rising/falling edge registers and with any duty-cycle issues.

In the end, the only use for DDR registers is for IO pins. Keep in mind that for FPGA designs, the hardware already exists. A good design will be one that makes use of the FPGA resources that actually exist vs any theoretically better design that doesn't actually fit the existing tech.

I suspect the tools just flag this as an error instead of emulating it using multiple registers and a mux.

 

[FvM]

FPGAs have very few DDR registers. They are only used for IO pins.

The dedicated DDR input and DDR output registers aren't flip-flops clocked by both edges. They are combinations of two DFF and a mux to either split a DDR input signal into two SDR signals or combine two SDR output signals into a DDR output signal.

It's possible under circumstances to emulate a dual edge sensitive DFF by a combination of two DFF and additional logic, including latches. It's not done automatically by the synthesis tools and timing closure will difficult. So the general suggestion is: don't do it.

 

[ads-ee]

Your first two code samples do not match any flip-flop that exists and therefore won't synthesize.
The first sample responds to both edges of the clock, there is no such FF.

The second version of code responds to an edge then decides the level of that edge with a mux, that doesn't exist in the real world either, so can't be synthesized.

Finally the last one is attempting to describe a DDR FF that can only be done if the signals a and b are on an output pin of the design. If wanted an internal node with a DDR output (not recommeneded, use a 2X clock as suggested by others), then you would have to have different output signal names for a and b rising and falling outputs (e.g. a_rise, b_rise, a_fall, b_fall). Finally you use a multiplxer with the clock as the select to generate the a and b outputs.