Peak voltage on switching NMOS.

[juanMco]

Hello everyone!

I am having some trouble with a charging/discharging capacitor circuit. Here I attach the basic circuit:



The "control" signal is a square wave from a 555 timer with period T=10 ms and TH= 250 uS to set up the switching for the transistor. "Vin" is the charge voltage for the capacitor (2 V in this simulation) and R9 sets the RC constant.

I need to charge/discharge the 10nF capacitor to generate a pulse (the original circuit has another capacitor to do the discharge pulse). When simulating the circuit with commercial transistors (NMOS and BJT), I see some peaks on the voltage exactly on switching times (testing on TP).



I need to reduce this peaks to ZERO or uV range. What kind of changes can I do on this circuit? I tried a lot of different transistors with low parasitic capacitances values but these peaks are always there. Thanks in advance.

Regards.

 

[FvM]

The effect is called charge injection and is normal behavior with any MOSFET switch. In the present circuit it's caused by Cgd.

Possible measures:
- use MOSFET with smaller area and respective lower capacitance
- use CMOS switch topology that achieves at least partial compensation of injected charges

 

[juanMco]

Hello,

Yeah I understood the charge injection and I am already testing CMOS switch topology.

I have better results but still mV range peaks on the output. With Vin =2 V is a low one and can work but in the final circuit I will have also Vin=10mV.

I will try now to find a MOSFET with very low Cgd.

¿Do you have maybe another idea with BJT topology or some different circuits?

Thanks in advance,

Regards.

 

[crutschow]

Look for a CMOS switch with the lowest charge injection.