Grid tie inverter PLL control method

[electrophysics]

Hi!

I'm designing a grid tie inverter. The important thing is it's synchronization with grid sinusoidal waveshape both in phase and frequency. I was planning to use PLL 4046B IC who will be given power from Vdd = 5 VDC. I'm not used to PLL so much so my thinking was that it will generate a sinusoidal wave of same phase and frequency as input grid reference sample and with this plus point that its output from VCO will be again "sinusoidal" with advantage that it will have constant peak to peak amplitude of 5 V always. Well when I designed the PLL circuit on breadboard to check it and I saw that though the output was in phase and same frequency as input sinusoidal but instead of sinusoidal waveform it is generating 50 Hz square wave of 5 V pk to pk amplitude at VCO output.

From this experiment I think that the purpose of using PLL is only to produce zero cross detection signal which is in phase with reference sinusoidal signal. But if I use input reference signal of proper amplitude as input to a comparator I can still generate zero cross which I can give to a microcontroller who will generate SPWM in either case.

My question is how I can generate a "sinusoidal" signal of amplitute 5 V pk to pk always which is in phase and same frequency as grid sinusoidal. "Because this way it can distinguish between change of grid phase to change of grid voltage amplitude". and I want to give that input to microcontroller to produce SPWM.

My other question if the purpose of PLL is only to produce zero cross detection then what is advantage of using PLL instead of low amplitute input grid signal given to a comparator zero cross circuit connected externally to microcontroller who will then produce SPWM in either case.

 

[nikhilmahasvar]

Kindly refer microchip website they have given a complete reference design with source code. You could gather lot of info from there.

 

[electrophysics]

Kindly refer microchip website they have given a complete reference design with source code. You could gather lot of info from there.

I have already gone through those application notes namely AN1338 & AN1444. However could not understand the answer to my these two questions.

 

[KlausST]

Hi,

I was planning to use PLL 4046B IC who will be given power from Vdd = 5 VDC. I'm not used to PLL so much so my thinking was that it will generate a sinusoidal wave of same phase and frequency as input grid reference sample

"my thinking" ...
--> you should read the datasheet.. It generates logic output signal. Not sinusoidal.

A complete PLL (in my eyes) uses:
* a digital reference clock input
* a digital reference clock divider ( with ratio "D")
* a VCO
* a digital VCO clock divder (for the feedback, with ratio "M")
* a phase comparator
* an analog low pass filter.. to get an analog signal from digital phase_comparator output. This is the analog input for the VCO.

Then the PLL may generate frequencies. f_PLL = f_ref * M / D

the problem with a 50Hz input signal is, that the "update rate" for the phase comparator and filter is very low.
This may lead to following problems.
* bad line frequency tracking
* PLL frequency jitter
* PLL loop instability.

Therefore you need to carefully desing the analog filter.

***
I did something similar:
Instead of phase comparator I used the capture_periferal of a microcontroller.
Then I did the filter calculation in software
And used an DAC (* edited) to control the VCO anlog input.
The benefit is a more flexible filter design. (I find it more handy to change software than to solder filter components)

****
But before all that ... you need to know what you want to do with the PLL frequency and what freqeuncy you need.

Klaus

 

[schmitt trigger]

The way I've seen that a PLL is used in these type of applications is as follows:

-You are going to synthesize the sinusoidal waveform, utilizing varying PWM.
-The PWM coefficients are stored in a lookup table. How many values per a full 50 Hz cycle depends on the design, but for simplicity's sake, let's say 100 samples.
-you then run a master clock at 100 times the output frequency (5000 Hz) addressing each individual coefficient.

So far so good...you have synthesized a stand alone 50 Hz sinewave (after some filtering, of course).
But if you connect that directly to the mains, the circuit will most likely short circuit explode as it is not synchronized.

That is where the PLL comes in. It will allow you to synchronize in frequency and phase your master clock to the powerline.
The key is that the master clock should be adjustable via a control voltage, i.e. a VCO, which is a key PLL building block.

Once that you build a PLL utilizing the elements that Klaus has described, utilizing the powerline as your "reference" and the PLL has acquired "lock", you then may connect the powerline and your synthesized sinewave together (assuming their respective voltages also match). The reference comes from the zero crossing pulse.

I'm not as proficient as Klaus is with microcontroller software, so I always design analog PLLs. What Klaus mentions about the loop settling time is true. The way I've minimized it is 1.) always use damping in the loop filter and 2.) restrict the VCO's frequency adjustment to a narrow range. For instance, a range of 4900 to 5100 Hz.

Parting ideas: A robust zero crossing circuit is an absolute must have. Electrical noise, for which powerlines are always full of, may produce erroneous pulses which can wreak havoc in your PLL.

 

[electrophysics]

Instead of phase comparator I used the capture_periferal of a microcontroller.
Then I did the filter calculation in software
And used an ADC to control the VCO anlog input.
The benefit is a more flexible filter design. (I find it more handy to change software than to solder filter components)

I think you mean DAC and not ADC here?

- - - Updated - - -

-You are going to synthesize the sinusoidal waveform, utilizing varying PWM.
-The PWM coefficients are stored in a lookup table. How many values per a full 50 Hz cycle depends on the design, but for simplicity's sake, let's say 100 samples.
-you then run a master clock at 100 times the output frequency (5000 Hz) addressing each individual coefficient.

So you mean that I take VCO output and let's say give that to some sort of ripple-carry binary divider like CD4040B. it will divide VCO output by 100 times. I will then AND operation of its output equivalent to 100 divider and then give output of AND gate to PLL phase detector input. Thus VCO output will then generate 5000 Hz.

- - - Updated - - -

Parting ideas: A robust zero crossing circuit is an absolute must have. Electrical noise, for which powerlines are always full of, may produce erroneous pulses which can wreak havoc in your PLL.

Does that mean if I use a comparator to detect zero crossing and give it's output to PLL reference signal input pin then it will have advantage that it will handle noise better than if I give direct mains sinusoidal input to reference signal input pin?

 

[KlausST]

Hi,

I think you mean DAC and not ADC here?

Sorry. Yes, it should be DAC.

****
Again you talk about sinusoidal signals. There aren´t any sinusoidal signals.
None of the datasheets I checked talk about sinusoidal signal.

***
You are talking about "PLL reference signal input pin". I don´t find this in the datasheet.
*Do you mean the digital input for the phase comparator, or the analog input for the VCO? (Which is far away from being sinusoidal. It`s more DC like)

Klaus

 

[schmitt trigger]

So you mean that I take VCO output and let's say give that to some sort of ripple-carry binary divider like CD4040B. it will divide VCO output by 100 times. I will then AND operation of its output equivalent to 100 divider and then give output of AND gate to PLL phase detector input. Thus VCO output will then generate 5000 Hz.

No AND is required......just feed the divider output back to the phase comparator. Please google PLL app circuits so the frequency multiplication theory is crystal clear to you.

And yes, a voltage comparator with hysteresis is a must to obtain a clean zero crossing signal.

 

[electrophysics]

Once that you build a PLL utilizing the elements that Klaus has described, utilizing the powerline as your "reference" and the PLL has acquired "lock", you then may connect the powerline and your synthesized sinewave together (assuming their respective voltages also match). The reference comes from the zero crossing pulse.

Does this implies that to make the design simple, if I'm using a 2 stage GTI where first stage boosts the voltage and 2nd stage uses a full-bridge configuration to produce sinusoidal waveform and if I use current limiting resistor (which will drive a feedback optocoupler) at the bottom mosfets source side of this full-bridge then this will create a constant current source type condition. So voltages will also match depending on the current sense limiting resistors who on the other will depend on the maximum power we want to take out from our GTI?