ERC Error in Calibre, Check PATHCHK

[milad_f1]

Hi,
In one part of my design which is DRC and LVS error free, I get this ERC Error: "Check PATHCHK_NPWRGND". The schematic and layout of the circuit is shown below. Selecting the error (number "1") in Calibre LVS window highlights the node which connects all the components to each others. Is it a known thing? Can I ignore this message?

I've noticed that I mostly get ERC errors like above (or PATHCHK_GND or PATHCHk_PWR errors), wherever there is a node in my circuit which has no path to VDD or GND, like above example or another example is on a node which connects two series (cascode) NMOS transistors (source of M1 to drain of M2). Is it something that I need to change in my LVS rule file or am I doing something wrong in my design?

Any help would be greatly appreciated.

Thanks.

 

[erikl]

Maybe VDD and GND aren't known global terminals (VDD! and GND! usually are). Try It!

 

[milad_f1]

Thank you erikl for your reply. I tried it but didn't work. Still same errors.

 

[milad_f1]

One of my friends told me that there might be something missing in my Calibre's rule file, like correct defining of Vdd or GND, and suggested me to do the ERC check with Assura. I did it and no ERC error/warning was found by Assura. As my layout is ERC error free in Assura and I am sure that my layout it correct, I think I can ignore these errors in Calibre but still eager to know how to fix it in Calibre.

 

[erikl]

Some more ideas:

1. Forgotten contacts between diodes and the ME1 to VDD/GND connection (or vias instead of contacts). Very unlikely - and I'd suspect that Assura would have recognized it, too.

2. Try and check your Calibre ERC rules' file for this very error. Perhaps you can find more info about its layer-dependent formation history.

3. What about the LVS check? Is it error-free?