Why does clock latency need to decrease?

[identical]

If clock latency is the difference in clock arrival at a particular flop compared to the clock source then why do we even care about latency.

for eg : if skew is 0 at latency 500 ps (500ps for both launch flop and capture flop) then why would it even factor in setup or hold violations since it is the same for both flops. The skew may vary.

 

[ThisIsNotSam]

it is not that simple, latency is not a 'single number', it is a 'range' because of variation.

say flopA has a latency of 5, meaning there are 5 inverters on the clock tree path that leads to flopA. Now say flopB has a latency of 5 as well, but the inverters are different. In theory, you would think the clock signal would arrive at the same time at both flops. In reality, all of these inverters will behave slightly different because of variation. You need best case and worst case scenarios for launch and capture.

that is why your goal should be to minimise latency and skew. they are both correlated and cannot be assessed individually.