How many LUTs can create a 32:1 MUX?

[bchcodez]

I want to find out how many LUTs I need to build a 32 input MUX.

I know that a 6 input LUT for example can be used to map a 4:1 MUX. Is there a way to calculate how many LUT we need for N inputs MUXs? Also is there any common LUT size used in FPGAs (4LUT, 6LUT or something else?)

 

[KlausST]

Hi,

Just when I use your input....
then
for 32 inputs you need 8 pieces of 6 input LUTs (4:1 MUX)for the first stage.
Then you have 8 outputs.

then use 2 pieces of 4:1 MUX for the second stage

then one piece for the third stage.

Gives a total of 8 + 2 + 1 = 11 LUTs.

two address lines for the first stage
two address lines for the second stage
one address line for the third stage

a total of 5 address lines.
2^5 = 32.

Klaus

 

[bchcodez]

Hi,

Just when I use your input....
then
for 32 inputs you need 8 pieces of 6 input LUTs (4:1 MUX)for the first stage.
Then you have 8 outputs.

then use 2 pieces of 4:1 MUX for the second stage

then one piece for the third stage.

Gives a total of 8 + 2 + 1 = 11 LUTs.

two address lines for the first stage
two address lines for the second stage
one address line for the third stage

a total of 5 address lines.
2^5 = 32.

Klaus

Thank you Klaus, If i follow correct your example, then for a 64:1 Mux then we need 16 pieces of 6 inputs LUTs (4:1 Mux) for the first stage, then another 4 piece, and in the final stage one more. This give us a total of 21 LUTs and a total of 6 address lines (2^6) = 64

 

[KlausST]

Hi,

Correct.

Klaus

 

[vGoodtimes]

Also, some FPGA may have specialized resources. For example, the F7MUX, F8MUX, and F9MUX in Xilinx devices.

In ultrascale, a slice has 8 LUT6's, 4 F7MUX, 2 F8MUX, and 1 F9MUX. (F7, F8, and F9 MUXs are 2:1 muxes, and are named this way as they can be used to create 7, 8, or 9 input functions)

As a result of this, you can implement a 32:1 mux using 8 LUT6s + 4 F7MUX + 2 F8MUX + 1 F9MUX. Older Xilinx devices do not have the F9MUX.