how to interface ADC7656 with altera max

[panimalar]

I need an example verilog coding for parallel interfacing.I have very less knowledge about verilog coding and interfacing with FPGA.can someone help?

 

[dpaul]

You need to be much more specific in asking questions.

Which protocol should the parallel interface follow? What is the width of the parallel interface?
Which FPGA dev board are you using?

 

[panimalar]

You need to be much more specific in asking questions.

Which protocol should the parallel interface follow? What is the width of the parallel interface?
Which FPGA dev board are you using?

In the data sheet(AD7656) they have not given any specific protocol and I am Using Altera Max II and regarding width I dont understand what is width in parallel interface

 

[FvM]

In the data sheet(AD7656) they have not given any specific protocol and I am Using Altera Max II and regarding width I dont understand what is width in parallel interface

Clarifies that you need to learn more about digital logic to manage the project.

The datasheet actually explains a lot. The interface can be either configured as parallel 16 bit data bus or as three channel SPI. You have to implement either one or the other in MAX II. Both is basically possible.

You didn't yet mention how the ADC data will be processed in your programmable logic and what's their final target.

 

[panimalar]

Clarifies that you need to learn more about digital logic to manage the project.

The datasheet actually explains a lot. The interface can be either configured as parallel 16 bit data bus or as three channel SPI. You have to implement either one or the other in MAX II. Both is basically possible.

You didn't yet mention how the ADC data will be processed in your programmable logic and what's their final target.

sir,Actually they told to study the parallel interface(AD7656) timing diagram and the Altera max II CPLD has to generate those signals to ADC(AD7656).This is the information they gave me.And I really dont know what to concentrate and where to concentrate also.

 

[mfro]

sir,Actually they told to study the parallel interface(AD7656) timing diagram and the Altera max II CPLD has to generate those signals to ADC(AD7656).This is the information they gave me.And I really dont know what to concentrate and where to concentrate also.

Did you read the datasheet, actually?

Apparently, there is no timing you need to care about, the interface can be completely asynchronous.

You initiate a converstion and then just wait until BUSY deasserts which signals converted values available.

Really simple.

 

[dpaul]

This is the information they gave me.And I really dont know what to concentrate and where to concentrate also.

So many "they"s. Is this project forced on to you?

Best way would be to take it part by part.
1> Learn more about Altera Max (read datasheet)
2> Then concentrate how the FPGA is communicating with its peripherals. You focus should be either of the one interfaces as explained in post #4 (read protocol datasheet)
3> Lean about AD7656 as to how it communicates (read datasheet)
4> Before beginning with Verilog............

I have very less knowledge about verilog coding

start with simpler stuff such as an up-down counter.

1. 2. 3. can be done in parallel to 4.

 

[panimalar]

Did you read the datasheet, actually?

Apparently, there is no timing you need to care about, the interface can be completely asynchronous.

You initiate a converstion and then just wait until BUSY deasserts which signals converted values available.

Really simple.

I am quiet confused with one particular thing.I was instructed to write the coding for the timing diagram (Parallel interface) of AD7656.My doubt is the in the timing diagram the last signal is the transfer of databits DB0 to DB15.But the diagram portrays as if it is sending analog signals such as V1,V2,V3,V4,V5,V6.How to read this analog signals using verilog?

 

[panimalar]

Clarifies that you need to learn more about digital logic to manage the project.

The datasheet actually explains a lot. The interface can be either configured as parallel 16 bit data bus or as three channel SPI. You have to implement either one or the other in MAX II. Both is basically possible.

You didn't yet mention how the ADC data will be processed in your programmable logic and what's their final target.

Sir The project is a part of the sonar receiver.Where the receiver receives Sound waves as input and those sound waves need to be transferred to digital. For this purpose A FPGA and ADC is used.The receiver is an hydrophone array.

 

[KlausST]

Hi,

But the diagram portrays as if it is sending analog signals such as V1,V2,V3,V4,V5,V6

Here V1... just represents the channel number, but the data(format) is digital.

Klaus

 

[panimalar]

if V1 is just the channel number then how many bits that it contain? and If possible can someone give me an example program for parallel interface

 

[KlausST]

Hi,

There are 16 individual data lines...
The ADC is called 16 bit ADC...

Can you imagine any other number than 16?
(The ADC theoretically could make it complicated and slow and use the 2 x 8 bit mode - figure 26. I don't recommend this)

*******
The parallel interface is as simple as can be: just a 16 bit DFF for each channel.

If this is a problem for you you should decide to start with more simple FPGA projects.
* input a single pushbutton with the use of a single DFF
* input four pushbutton with a quad DFF
* input 16 ADC data lines with a 16xDFF

Or do you see the problem in setting up an FSM to generate the ADC control signals?

Klaus