ESD protection on Differential Amplifier Amp circuit's input

[eengr]

Hi there
I am currently working on a design of a product. The product will take inputs from a remote sensor and log them on board. It has a micro-controller based circuit that will perform logging and other user interface functions.

The board has several inputs as 420mA input, sensors input (analog signals) , RS485 / USB interface etc. I have not included the full schematic here as it will make the whole message and picture size very big and the area I am concerned about is only a small portion of overall circuit.

The product is 24V DC (12V – 30V DC full range of input DC power) powered and has on-board voltage regulation to bring the voltage down to +5V & +3.3V Rails

The board will have terminal block (phoenix connector) type interface to outside world
https://www.phoenixcontact.com/online/portal/gb?uri=pxc-oc-itemdetailid=1840502&library=gben&pcck=P-11-02-11&tab=1

and whole assembly will be mounted in DIN rail type enclosure. This would mean that screw terminals on terminal blocks connections will be exposed to outside world with No mechanical cover around the screw terminals.
This product will go through EMC testing for compliance and the test I am concerned about is ESD. The standard required the Contact discharge to be +/- 6kV and Air discharge to be +/-8kV. This charge voltage will be applied directly to the screw terminals where the interface is done between the PCB of said product and the outside world.




For one of the sensor interfaces I am using a differential amplifier circuit with LOW Pass filter at the input as shown in the attached picture. The inputs ‘SIG_POS’ and ‘SIG_NEG’ are connected directly to two points on screw terminal block. These points will be tested for ESD protection hence subjected to +/-6kV contact discharge & +/-8kV Air discharge.
The output ‘SIG’ is connected to ADC (for info only No questions on output side + there are rail decoupling caps on 5V rail of op-amp not shown in schematic). The analog signal coming in NOT very fast changing signal. So speed is not an issue. We sample it once every second

My question is that would this circuit be safe to handle the ESD test without damaging anything in the area shown in schematic OR would I need to add more OR different components. The ESD voltage level will be applied directly to the points marked as ‘SIG_POS’ & ‘SIG_NEG’. I have added the details of all the parts used next to schematic. My thinking was that the combination of R104 & R105 being 10K resistors & C102 & C104 of 10nF /50V caps would take the initial energy out of the ESD pulse and keep the rest of circuit safe. I don’t know what exact formulae to use to get the correct values for bringing the ESD level to safe levels using the Resistor/ Capacitor combination. Also I am not sure if using small 0402 packages would be good enough OR should I be using bigger footprint packages. Any expert help would be greatly appreciated as I want to fix these issues at this stage of the design instead of taking it to EMC test lab and then finding out that practically these components should have been different size or values.

 

[FvM]

For full ESD strength, you'll place bidirectional zener or TVS diodes at all in- and output exposed to the outside.

Without frontend EDS protection, 0402 parts will obviously break over at much lower voltage level, but even large parts like 1206 aren't safe against damage by ESD, although at least the resistors have a considerable larger energy handling. Capacitors below 10 nF are at risk to be charged above rated voltage by a single ESD pulse.

 

[eengr]

Thanks for the feedback.
Am I right in understanding that if I have a TVS diode of say 5V or 12V e.g.,

https://www.farnell.com/datasheets/661407.pdf?_ga=1.44487460.1274920303.1461313993

at the nodes 'SIG_POS' and SIG_NEG' to GND then I could use rest of circuity as it is without the need to change the resistor or cap packages? OR would I still need to change them to 1206ish packages.
The manufacturer of proposed TVS claims to meet the contact >8kV in the data sheet which I am assuming directly across the TVS without any additional series resistors!

 

[FvM]

Yes, TVS diodes without additional series resistors. TVS voltage depends on the maximum input voltage and should be selected so that the TVS diode can't be burned in normal operation. If you expect e.g. 24 DC, it should be chosen respectively.

You can keep the 0402 parts if appropriate.

 

[eengr]

That's great news. Thats almost sorted for diff amplifier side of circuit. Only thing left is that I am bit concerned about the Power Input ports, (e.g., for 420mA loop).
My understanding for using a capacitor on Power Lines for ESD protection is that:

V(final) = C(esd) x V(esd)
--------------------------
C(protect) + C(esd)

We know C(esd ) = 330pF & V(esd) = 8kV

For C(protect) of 100nF , this yields:
V(final) = 26.313V

I have chosen C205 in picture below as 100nF/50V/0603 version


From the above calculations (this is a formula I found via internet search) I think that this Power input could be protected against ESD by using 100nF cap and might get away without using the TVS for this port. - Please correct me if I am wrong.

Second. should I be putting this ESD protection for Power ports after the Fuse (as shown in schematic) OR on input of Fuse (the port connected to outside world) . In other words would a fuse require ESD protection as well?
Fuse I am using is: F103 = 62mA - Farnell: 1832080 - Littel Fuse - 0459.062UR

https://www.farnell.com/datasheets/611632.pdf?_ga=1.105773955.1274920303.1461313993

I am not sure which spec in the fuse datasheet would I need to check. Not sure about the standard practice for placement of this ESD protection component on Power port especially for the case if there is Short circuit on this component which is on Input side of Fuse but directly across customer's power supply (Or am I thinking too much here?)

 

[FvM]

I agree with the 100 nF calculation. Similar calculations are usually applied for parallel RC circuits connecting shield and circuit ground.

The design of power supply inputs should consider surge and similar EMI, also possible overvoltage and power reversal.