Have you read PG153, specifically pages 19 & 22? The signals are describe for both of these.
don't know about this, I would have to attempt to implement this design, which I don't have time to do. Though each of these signals are likely the tri-state controls for their corresponding pins of the _o pin. I other words you are probably supposed to be instantiating tri-state (OBUFT) primitives for these outputs and these signals drive the tri-state control.
The one called spi_flash is the spi interface. I'm not sure why you have this question. Maybe you don't know that this IP can be used for controlling the SPI configuration flash or as a standard 4-wire SPI master. Perhaps you are not configuring the right version?
It's controlled via the AXI4-Lite interface and the base address can be found in the Address Editor tab.
Hi, I am looking for 4 wires(CLK, MISO, SIMO, SS) SPI to read the output and give the command to system(microblaze) from outside like UART Terminal and surely not SPI configuration flash.
Study the SPI IP spec carefully, it would be written there how these pins can be connected (don't have time to read the spec and extract that info for you).
On top of what ads-ee has said, I would like to add that the *_t signals looks like tri-state buffer control signals and they cannot be connected directly to an FPGA i/o port. Use an OBUFT as ads-ee has mentioned.
I think you are using the correct IP.
Hi,
/**
* Fetch input from UART then callback voip_contrl_app to
* process the selection
*/
#include "xuartlite_l.h"
void get_voip_ctrl_app_input(void)
{
if (!XUartLite_IsReceiveEmpty(STDIN_BASEADDRESS)){
inchar = (u8)XUartLite_ReadReg(STDIN_BASEADDRESS, XUL_RX_FIFO_OFFSET);
xil_printf("%c\n\r",inchar);
voip_ctrl_app(inchar);
voip_ctrl_app(CARRIAGE_RETURN);
}
}Have you read the chapter "Testing the Example Design on a KC705 Board" in the pg153-axi-quad-spi.pdf document? There seems to be some info there!
Keep it simple. Just read-from/write-to valid AXI addresses.
#include <stdio.h>
#include "platform.h"
#define LOC3 (*(unsigned int *)0xf0000000) // This is the axi address
int main()
{
init_platform();
LOC3 = 0xcafeface; // Write data "cafeface" to LOC3
cleanup_platform();
return 0;
}This is the xdc file generated after adding spi ip :
Hi,
ENTITY system_basic_axi_quad_spi_0_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
cfgclk : OUT STD_LOGIC;
cfgmclk : OUT STD_LOGIC;
eos : OUT STD_LOGIC;
preq : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END system_basic_axi_quad_spi_0_0;OBUFT #(
.IOSTANDARD("DEFAULT"),
) OBUFT_inst (
.O( io0_o ),
.I(XADC_GPIO_0),
.T( io0_t)
);The SPI module you are trying to add won't support what you want to do. The SPI module is a MASTER ONLY module, a master on the AXI controls the slave interface of the Quad SPI to control a master SPI to communicate with an external slave SPI. You want to use this as a terminal to control the FPGA which won't work.
Code VHDL - [expand]
Hi,
This means at least for this purpose how I am proceeding above is right?
If you connect an IO buffer b/w the quad_spi ports and an FPGA IO pin then you are good to go.
It is written in the spec.
Now its deviating from the original topic. Please create a new thread for your new Q.
To answer that, I have to read the spec in details as to how it behaves. Sorry don't have time for that!
