Common centroid for differential pair..?

[Ranjithgaruda]

Why common centroid technique preferred for differential pair..? if you say it eliminates linear gradients then
1. Please explain what are the linear gradients and which type of mismatch category will it fall..(random/systematic)..
2. How exactly is this common centroid fighting against these linear gradients..?
3. If you can... please stick to qualitative answers(i mean by simple words) rather than posting a random link which has quantitative analysis approach..

A Ton of gratitude..

 

[erikl]

1. To a 1^st-order approximation, linear gradients are produced by stress. The effects of stress can be quantified in terms of piezoresistivity, or resistivity change, generating systematic mismatch.

2. Compensation of linear gradients in both axes (x and y) by strict observation of these 4 rules:

 

[dick_freebird]

Temperature gradients also affect matching strongly.
Not so much a problem in subthreshold CMOS analog
with output loads all on-chip, but put a 50mA output
stage / heater at one side of the chip and you have
some application-variable offset contributors that
want beaten down.

 

[Juan Jose Carrillo]

Do the dkit mismatch models work correctly when resistors which should be matched are not in common-centroid layout?

For example, a coleague designed a bandgap reference, and its design has three resistors that should be matched, but when he draw the layout, he put the three resistors in thi way. R1 R2 R3 (R1, R2 and R3 are made up of fingers).

Thanks in advance

 

[dick_freebird]

You'd have to drill into the foundry modeling group
to ask what the characterization material, that the
mismatch models are extracted from, looked like. In
my experience match data was taken from matching
structures that had identical, adjacent, but not
interleaved (as CC would) resistors, MOS, BJT devices.

So there could be further improvement by CC if the
matching stats are for non-CC style layouts. And the
improvement to things like temperature gradient
effects (never an issue with simple low current
individual device value measurements) of course is
there (and likely unmodeled entirely, thermal effects
capability seems kind of recent in simulators and
PDKs always lag behind that).