How to get ther intraction between different subsystems...

[velu.plg]

i need to know how to get the interaction details between different subsystems because am going to floor plan my design.
tool used : vivado 2014.4

 

[TrickyDicky]

Most people use simulation...

 

[velu.plg]

The purpose of the above question is if two subsystem communicate often in the sense i need to place this two as much as nearest.

 

[TrickyDicky]

Just because they communicate often doesnt mean they need to be close to each other on the chip. If they communicate often at 25Mhz then they could be on opposite sides of the chip and still probably meet timing.

Why are you trying to do floor planning? this should only be needed if you are struggling to meet timing.

 

[velu.plg]

Just because they communicate often doesnt mean they need to be close to each other on the chip. If they communicate often at 25Mhz then they could be on opposite sides of the chip and still probably meet timing.

Why are you trying to do floor planning? this should only be needed if you are struggling to meet timing.

Exactly! my design doesn't met timing.we have 16 subsystems which have around 40 clocks

 

[dpaul]

The purpose of the above question is if two subsystem communicate often in the sense i need to place this two as much as nearest.

Can't you set commands in the XDC to specify placement of the cells?
ug903 - see Pg62 "Placement Constraints"
I can't be any more specific as I have never used such type of Constraints!

btw-

we have 16 subsystems which have around 40 clocks

:shock:
OMG - Is this an SoC of SoCs design (can't help but be curious)! That's all I can say!

 

[ads-ee]

I've worked on FPGA designs with nearly that many clocks before, 30+. Most of the problems with that many clocks is the number of control sets you end up with. Every combination of clock, reset, and clock enable results in a new control set. Minimizing those may actually help place and route and timing closure.

Some advice is to reduce the number of resets to only reset critical control logic avoid any resets on the datapath unless those signals affect control logic. Avoid enables if you can just let the pipeline run without stopping it (I know sometimes that can't be done).

Floor plan the logic that is at the highest clock frequency and try to isolate it to a single clock region if possible (i.e., try not to overlap two clock regions if it fits in one. Don't try and create placement constraints for everything, the tools will likely do a much better job if you just do the minimum of placement constraints to give the tools a good starting point.

 

[slutarius]

Exactly! my design doesn't met timing.we have 16 subsystems which have around 40 clocks

You probably need to check the IO assignment. It contributes to timing result also.