Explanation Required for High Power Switching Power Supply (3-60v 40 Amps)

[adnan012]

hi,

I need explanation for the switching supply (attached circuit diagram).

What is the topology used in this design?
What is the purpose of D7 and D7'?

 

[treez]

it is a 2 transistor forward converter.
There is no power factor correction stage before it.
There is no mains fuse, which is bad
The current sense transformer has been done wrong, there is no means to reset the current sense transformer.

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there is no isolation pri to sec.
I don't know why they bothered to used an isolated bias supply, when there is no isolation in the main converter.

 

[adnan012]

I think it 220 mains is isolated from isolated supply and ouput?
How Current transformer is reset?

 

[treez]

The gate drive is original, the reset voltage on the GDT is 24V, and the rail is 17v, so there will be a short interval, just before the igbt's are turned ON, where the igbt gates are only being pulled down by the gs resistor, and the sec of the GDT will be ringing and could possibly spuriously bring the igbts on unwontedly...id get round that by making the lower igbt direct drive.

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you reset the current transformer by putting a resistor across it, or a D/zener series combination.
Regarding the CST secondary voltseconds OFF must be at least equal to voltseconds ON to get reset

 

[Warpspeed]

I think it 220 mains is isolated from isolated supply and ouput?
How Current transformer is reset?

There is no mains isolation.
One side of the incoming mains (U2) is directly connected to the negative dc output.
Pretty dangerous if active and neutral are reversed.

The current transformer will reset fine in this circuit, because of the series diode D9 with the 1K resistor R16 across it. The reverse voltage across the CT will be much higher than the forward voltage.

The CT sees 3R3 plus the diode in the forward direction, and 1K + 3R3 in the reverse direction. Definitely no problem with the CT.

 

[adnan012]

I am trying to understand it

"The gate drive is original, the reset voltage on the GDT is 24V, and the rail is 17v, so there will be a short interval, just before the igbt's are turned ON, where the igbt gates are only being pulled down by the gs resistor, and the sec of the GDT will be ringing and could possibly spuriously bring the igbts on unwontedly...id get round that by making the lower igbt direct drive."

Kindly explain it in more detail.

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Is there any simulation available for current transformer?

 

[KlausST]

Hi,

One side of the incoming mains (U2) is directly connected to the negative dc output.

U1 is directely connected to mains.
But i can´t find where U2 is connected to mains.

Klaus

 

[treez]

woops, Warpspeed is right about CST, I overlooked R16
It does depend on the Lsec value of CST though......because voltS ON (max) is 2V ...so you need really to be generating at least 2V across R16 in the off time (and more that that really so you get a saftety margin) ......so you need 2mA of magnetising current to be flowing through r16...and of course, this depends on the LSEC value of the CST.....if LSEC of CST is really high, then there wont be much magnetising current developed in LSEC, and you might not get enough reset voltage across r16...so r16 may need to be higher value depending on the LSEC value of the CST

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Is there any simulation available for current transformer?

You can sim both GDT and CST in ltspice which is free

 

[mtwieg]

Hi,



U1 is directely connected to mains.
But i can´t find where U2 is connected to mains.

Klaus

Correct. The controller (biased by U2) is on the output side, with both being isolated from the mains (U1).

 

[treez]

indeed, I have been thrown by the fact that the drawing format is similar to other drawings where the controller is referenced to the post mains bridge dc bus.
This reminds me of an interview where they drew a non-inverting opamp circuit to me, and drew it in the 'normal format' of a inverting opamp, and showed it to me from a distance, I then blurted out "non inverting", and of course was completely wrong.

 

[Warpspeed]

The drawing layout is definitely a bit strange and rather difficult to follow, unless you expand all the detail, which I failed to do first time.

Mtwieg is quite correct, mains isolation is provided by transformer isolation.

 

[adnan012]

Thanks for reply.

In the Schematic current is sensed at the primary side, how can it be related to the secondary side?

Can i use shunt resistor at the primary side (it will effect the isolation)?
How current transformer is constructed using ordinary (unknown) toridal core ?

 

[FlapJack]

This schematic was drawn by Marque de sade.

 

[treez]

In the Schematic current is sensed at the primary side, how can it be related to the secondary side?

its called current mode control. Its "related" to the secondary side because the current goes through the primary, then passes as flux though the transformer, then gets into the secondary, so its "related"

Can i use shunt resistor at the primary side (it will effect the isolation)?

As long as you rc filter it into the cs pin .

How current transformer is constructed using ordinary (unknown) toridal core ?

try and wind secondary evenly spaced round the whole core, then pass the primary through the torroid.
Or just use a ETD type core. again, try not to bunch the secondary up.
Ideally if using a torroid type you use a small hole toroid as possible, so the primary goes near all the secondary turns.

 

[adnan012]

what is the relation between no of turns and generated voltage?

 

[treez]

the voltage generated at the secondary is equal to I*R + Vf(diode)

I = I(PRI)/(NP/NS)
R = burden resisrtor

this is for a unipolar CST.
YOU SHOULD TRY AND KEEP the voltage across sec during pri conduction as low as possible

 

[adnan012]

Do i need PFC stage for this supply?

 

[Warpspeed]

Not if its for yourself, only if you are planning to manufacture them as a commercial product.

 

[adnan012]

ok.

At this power level which topology is used in PFC?

 

[treez]

If you don't do a PFC stage, and your power level is much more than about 80W, then you will find that you will need so much input capacitance, (so as to manage the ripple current), that your input current is consisting of very high, short pulses of current, which , though fuse datasheets say they can manage this, the fuses tend to nuisance trip under these circumstances, meaning that you may need the pfc stage after all.