How to monitor the design status while performing Partial Reconfiguration?

[msdarvishi]

Hello everybody,

I designed and implemented an 8-bit microprocessor including ALU, Program Counter, Accumulator, Memory, Instruction Register and MUX modules. I partially reconfigured ALU and Program counter. My concern is that the implemented design must be on-the fly (must not STOP) while one module is partially reconfigured. Can anybody tell me is there any tool to monitor the hardware status real-time while the partial reconfiguration is done? Does the ChipScope is helpful and how?

Also, I am using the Xilinx Gensys board containing Virtex-5 FPGA (XC5VLLX50T).
I use ISE 14.7 for implementation and VVHDL coding and PlanAhead 14.7 for implementation of Partial Reconfiguration.
The bitfiles are also created with planahead. I want to know how can I monitor the status of my design in real-time while one module is partial reconfigured.
Bottom line, I am programming FPGA with Digilent software namely Digilent Adept Software or impact tool in ISE.


Thank you,

 

[mrflibble]

Step 1: Read the Fine Manual: www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug702.pdf
Step 2: Actually read it.