32x32 Single Cycle Fast Multiplier

[Mr.PAP]

I am looking for 100 Mhz multiplier in a single cycle area is not a problem(180nm ON-semi), (I tried sequential and booth).
I knew a method but I am not sure if it will reach that speed is the old method from 3rd grade:

P = multiplicand[31:16]
Q = multiplicand[15:0]
R = multiplier [31:16]
S = multiplier [15:0]

QxS, PxS, QxR, PxR
and than have to add them but it does not work, I am sure I am doing something wrong when I add them(I moved the carry too) but even though I don't know if it will reach the requirement.

Can anyone give me some hints/examples/Verilog ex code about such a fast multiplier?

 

[stanford]

I am looking for 100 Mhz multiplier in a single cycle area is not a problem(180nm ON-semi), (I tried sequential and booth).
I knew a method but I am not sure if it will reach that speed is the old method from 3rd grade:

P = multiplicand[31:16]
Q = multiplicand[15:0]
R = multiplier [31:16]
S = multiplier [15:0]

QxS, PxS, QxR, PxR
and than have to add them but it does not work, I am sure I am doing something wrong when I add them(I moved the carry too) but even though I don't know if it will reach the requirement.

Can anyone give me some hints/examples/Verilog ex code about such a fast multiplier?

So you want to do 32x32 with four 16x16 multipliers? You will need 3 additional adders but need to be careful with the bit positions when you set them up to add.

 

[std_match]

You must shift QxR and PxS left 16 bits before adding. PxR must be shifted left 32 bits.

 

[KlausST]

Hi,

Did you decide whether you want unsigned only or you want signed arithmetics?

Klaus

 

[Mr.PAP]

So you want to do 32x32 with four 16x16 multipliers? You will need 3 additional adders but need to be careful with the bit positions when you set them up to add.

The multiplication algorithm that I used does not matter it just have to finish the operation in 10ns, the method I posed above I saw in same cores from ETHZ and they said that this method is a single cycle although I have my doubts because I think they are doing something like:

Mul something
LW something
SW something
SLL something
No OP / stall
and now them save the result of mul in GPR

I am not 100% sure they are doing it this way, maybe this algorithm really work fast and single cycle as I said I did not implemented it yet I had some problems with the carrys when I added them number.

You must shift QxR and PxS left 16 bits before adding. PxR must be shifted left 32 bits.

I did that but the point it there are some carrys which has to be considered when you add 32b + 32b result can be 33 than when you add 32 + 31 result can be 33 than the 16b has te be added again and the result can be 17b, if you can explain in details the algorithm please do it.

Hi,

Did you decide whether you want unsigned only or you want signed arithmetics?

Klaus

I has to work for both cases.

 

[KlausST]

Hi,

I has to work for both cases.

--> You need different algorithms.

A unsigned 32 x 32 bit multiplication causes a 64 bits wide result
A signed 32 x signed 32 bit multiplication causes a 63 bits result. If you store it as 64bit result, then bit62 will be zero all the time.

Klaus

 

[Mr.PAP]

Hi,


--> You need different algorithms.

A unsigned 32 x 32 bit multiplication causes a 64 bits wide result
A signed 32 x signed 32 bit multiplication causes a 63 bits result. If you store it as 64bit result, then bit62 will be zero all the time.

Klaus

Can you give some short tips, what with what to mul and to add and how to play with the carrys and how to make it for signed too(just some algorithmical hints) please?

 

[KlausST]

Hi,

I never did a multiplier design.
But a 16 bit signed multiply is rather: 1_bit_sign + 15_bit_value.
Thus signed x signed = 1_bit_sign x 1_bit_sign = 1_bit_sign and 15_bit_value x 15_bit_value = 30_bit_value

Klaus

 

[Mr.PAP]

Yes but how do I compose the big number after I do this, how do I shift add move carry and then add the carry again?(if is signed number than only when it comes to check the up half the sign matters the down half can be just multiplier)

 

[jbeniston]

Perhaps a silly question, but did you just try synthesizing assign product = multiplicand * multiplier? Design compiler has some fairly decent implementations if you have a DesignWare license. (Make sure you do set_app_var synthetic_library "dw_foundation.sldb")

https://www.synopsys.com/dw/doc.php/doc/dwf/datasheets/dw02_mult.pdf

 

[Mr.PAP]

Perhaps a silly question, but did you just try synthesizing assign product = multiplicand * multiplier? Design compiler has some fairly decent implementations if you have a DesignWare license. (Make sure you do set_app_var synthetic_library "dw_foundation.sldb")

https://www.synopsys.com/dw/doc.php/doc/dwf/datasheets/dw02_mult.pdf

I don't have access there.