32bit timer problem in pic24ep512gu814

	#include <24ep512gu814.h>
	#include "REGISTERS.h"
	#include "PORT_BIT.h"
	
	#use delay(clock=25M)

	#pragma config ICS = PGD3           // ICD Communication Channel Select bits (Communicate on PGEC3 and PGED3)
	#pragma config JTAGEN = OFF         // JTAG Enable bit (JTAG is disabled)

	// FPOR
	#pragma config ALTI2C1 = OFF        // Alternate I2C1 pins (I2C1 mapped to SDA1/SCL1 pins)
	#pragma config ALTI2C2 = OFF        // Alternate I2C2 pins (I2C2 mapped to SDA2/SCL2 pins)
	#pragma config WDTWIN = WIN25       // Watchdog Window Select bits (WDT Window is 25% of WDT period)

	// FWDT
	#pragma config WDTPOST = PS32768    // Watchdog Timer Postscaler bits (1:32,768)
	#pragma config WDTPRE = PR128       // Watchdog Timer Prescaler bit (1:128)
	#pragma config PLLKEN = ON          // PLL Lock Enable bit (Clock switch to PLL source will wait until the PLL lock signal is valid.)
	#pragma config WINDIS = OFF         // Watchdog Timer Window Enable bit (Watchdog Timer in Non-Window mode)
	#pragma config FWDTEN = OFF         // Watchdog Timer Enable bit (Watchdog timer enabled/disabled by user software)
	
	// FOSC
	#pragma config POSCMD = HS          // Primary Oscillator Mode Select bits (HS Crystal Oscillator Mode)
	#pragma config OSCIOFNC = OFF       // OSC2 Pin Function bit (OSC2 is clock output)
	#pragma config IOL1WAY = ON         // Peripheral pin select configuration (Allow only one reconfiguration)
	#pragma config FCKSM = CSECME       // Clock Switching Mode bits (Both Clock switching and Fail-safe Clock Monitor are enabled)
	
	// FOSCSEL
	#pragma config FNOSC = PRIPLL       // Oscillator Source Selection (Primary Oscillator with PLL module (XT + PLL, HS + PLL, EC + PLL))
	#pragma config IESO = ON            // Two-speed Oscillator Start-up Enable bit (Start up device with FRC, then switch to user-selected oscillator source)
	
	// FGS
	#pragma config GWRP = OFF           // General Segment Write-Protect bit (General Segment may be written)
	#pragma config GCP = OFF            // General Segment Code-Protect bit (General Segment Code protect is Disabled)
	
//	int32 Period_value	= 70000000; // Instruction clock
	int8	count	=	0;
	
	void Timer2_3Interrupt() iv IVT_TIMER_3 ilevel 7 ics ICS_SRS        // SHOWING AN ERROR
	{
  	T3IF    = 0;
  	RJ12	= ~RJ12;
	}

	void Init_timer3_32()
	{
		T2CON	=	0;
		T3CON	=	0;
		TMR3	=	0;
		TMR2	=	0;
		T2T32	=	1;
		T2CS	=	0;
		T2GATE	=	0;
		T2CKPS_4=	0;
		T2CKPS_5=	0;
		PR3		=	12;
		PR2		=	13580;
		IPC2	= 	0X0007;
		T3IF	=	0;
		T3IE	=	1;
		GIE		=	1;
		
		T2ON	=	1;
	}

	void cpu_initiallisation()
	{
		PMD1	=	0X07FF;				// TIMER3 IS ENABLED T3MD = 0;
		PMD2	=	0XFFFF;
		PMD3	=	0X0FFF;
		PMD4	=	0XFFFF;
		PMD5	=	0XFFFF;
		PMD6	=	0XFFFF;
		PMD7	=	0XFFFF;
		
		ANSELA	=	0X0000;
		ANSELB	=	0X0000;
		ANSELC	=	0X0000;
		ANSELD	=	0X0000;
		ANSELE	=	0X0000;
		ANSELF	=	0X0000;
		ANSELG	=	0X0000;
		ANSELH	=	0X0000;
		ANSELJ	=	0X0000;
		ANSELK	=	0X0000;
	
		TRISA	=	0X0000;
		TRISB	=	0X0000;
		TRISC	=	0X0000;
		TRISD	=	0X0000;
		TRISE	=	0X0000;
		TRISF	=	0X0000;
		TRISG	=	0X0000;
		TRISH	=	0X0000;
		TRISJ	=	0X0000;
		TRISK	=	0X0000;

		INTCON1	=	0x8000;
		INTCON2	=	0X8000;
		INTCON3	=	0X0000;
		INTCON4	=	0X0000;

		INTTREG	=	0X0000;
		
	}
	void main()
	{
		
		cpu_initiallisation();
		Init_timer3_32();
		while(1)
		{
			RD1 = ~RD1;
			delay_ms(1000);
		}
	}