module top(clk, a, b, y);
input clk;
input [31:0] a, b;
output reg [31:0] y=0;
always @ (posedge clk) begin
y <= a + b;
end
endmodule
Timing report says:
Minimum Clock Period: 8.0ns
Maximum Internal Clock Speed: 125.0Mhz
(Limited by Clock Pulse Width)
Fitter Report says:
Design Name: top Date: 8- 2-2005, 11:21AM
Device Used: XC95144-7-PQ160
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
65 /144 ( 45%) 514 /720 ( 71%) 249/288 ( 86%) 32 /144 ( 22%) 33 /133 ( 25%)
** Function Block Resources **
Function Mcells FB Inps Signals Pterms IO
Block Used/Tot Used/Tot Used Used/Tot Used/Tot
FB1 3/18 34/36 34 44/90 2/17
FB2 10/18 33/36 33 74/90 5/17
FB3 6/18 33/36 33 68/90 3/17
FB4 11/18 33/36 33 79/90 4/17
FB5 9/18 33/36 33 73/90 3/17
FB6 10/18 32/36 32 67/90 6/16
FB7 8/18 18/36 18 52/90 5/16
FB8 8/18 33/36 33 57/90 4/16
----- ----- ----- -----
65/144 249/288 514/720 32/133
* - Resource is exhausted
** Global Control Resources **
Signal 'clk' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 64 64 | I/O : 96 125
Output : 32 32 | GCK/IO : 1 3
Bidirectional : 0 0 | GTS/IO : 0 4
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 97 97
<snip>
module top(clk, a, y);
input clk;
input [31:0] a;
output reg [31:0] y=0;
always @ (posedge clk) begin
y <= y + a;
end
endmodule
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?
We use cookies and similar technologies for the following purposes:
Do you accept cookies and these technologies?