abdalrahman_ehsan
Newbie level 6
Hi,
i am designing asynchronous FIFO with the following specs:
write clock = 166 Mhz
read clock = 66 Mhz
assuming reading and writing occur consequently each clock cycle for reading and writing
i am asking how to calculate FIFO depth ? i think i need at least 100 locations, is it right ?
one more question : what corner cases should i verify for proper functionality of the FIFO?
thanks in advance
i am designing asynchronous FIFO with the following specs:
write clock = 166 Mhz
read clock = 66 Mhz
assuming reading and writing occur consequently each clock cycle for reading and writing
i am asking how to calculate FIFO depth ? i think i need at least 100 locations, is it right ?
one more question : what corner cases should i verify for proper functionality of the FIFO?
thanks in advance