32 Channel Low Frequency DDS

[XMage]

Hi All

I have the following setup:
- System on Board (Raspberry Pi 2/3)
- PCB containing an AD5383 43 Channel +/- V DAC (12 bit)
- 24 vibrotactile actuators (currently) which have a max frequency of appro 2KHz (these are custom designed).

I've done a lot of reading about DSP/DDS as essentially this is a 32 channel DDS with the actuators being controlled with a varying voltage most often in the shape of a sine wave (they are basically low frequency speakers).

However, most reading I've done involves frequency ranges much higher than 2KHz.

For processing and performance reasons and the eventuality that all channels might produce different frequency/waveform/amplitudes at any given time I thought a Phase accumulator with Sinewave LUT (Look up table) was the ideal approach.

However I'm wondering about optimal selections of these?

Key values I have to work with are :
- 0 Voltage on DAC = 2048
- Oscillation point/Offset for the sinewave is 3072
- Therefore Max amplitude in applicable range is 1024
(NB actuators require the negative V outputs but are not used for active purposes)

I need good resolution on the amplitude control (approx every 8-16 values)
- Frequency control doesn't require as high resolution (about every 100Hz) but the higher the resolution the better.

Any advice would be most welcome.

Thanks in advance

 

[barry]

A DDS is a pretty straight forward approach, but you need 32 of them. You could probably share some resources, for example you could use a single sine look up table (LUT) for all 32 channels. It's not totally clear, but are you expecting to generate constant frequency signals? That would make things easier. There are two approaches you could use:

1) you have a counter that generates the address for the sine LUT. You use a second counter that is loaded with a value such that every time the counter hits the terminal count the address counter is incremented. This will give you the best sine wave resolution, as it will step through the sine table by 1, but it will limit your maximum frequency.

2) you increment the address counter by some fixed value every step. This way, when your increment value is larger you jump over more values in the LUT to get higher frequencies. Not as good resolution as (1), but you can generate higher frequencies this way.

Basically, you need to determine what your maximum clock rate is, what your minimum and maximum desired frequencies are, size of your LUT, etc. It might help to look at some actual DDS chips (Analog Devices) and see what their architecture is.

 

[XMage]

Max frequency required is approx 1KHz per channel
but I really need a nice smooth high resolution on each signal at whatever frequency is being generated so I am figuring that solution 1 would be most appropriate.

Given Nyquist theories I would also assume a LUT of 2KHz (512 samples for a quarter cycle) should be necessary?

My main concern though is minimising floating point calculations and ensuring easy manipulation of the amplitudanal values of the waveform. Oscillation offset is easy enough (twiddle the top bits of a 12 bit value to be 1 (ie add 3072)).

At present I have a 1024 value table (half cycle) with a max amplitude of 255
But I'm sensing that there might be a lot of the "on the fly" calculations required if this is not the required amplitude of the output signal.

Someone else tried implementing this with a vector of vectors of floats. This was so slow it was ridiculous and could not function properly beyond anything more than one cycle...

 

[FvM]

In usual DSP terms, DDS refers to the second (phase accumulator) method.

Unlike the first method, it's linked to a fixed sampling rate independent of generated frequency. A fixed sampling rating is a prerequisite for generating an effectively ideal sine waveform after the output reconstruction filter. Frequency resolution is virtually infinite (depends only on phase accumulator length).

For a processor implementation, you need to choose a sampling frequency above Nyquist rate (e.g. 5 to 10 kHz for 2 kHz maximal sine frequency) and implement a timer interrupt based DDS routine. For lowest phase jitter, the DAC load signal should be generated by a hardware timer output.

Processing 32 DDS instances at 10 kHz shouldn't be a problem for Raspberry Pi.

High order DAC output filters are however required. Alternatively use a higher sampling rate and lower filter order.