global clock gating problem

[u24c02]

Hi.

I try to global clock gating with

set_clock _gating_style
-sequential_cell latch ₩
-control_point before ₩
-control_signal scan_enable ₩
-minimum_bitwidth 3
-max_fanout 64
-num_stage 1
-positive_edge_logic {integrated}
...
...
compile_ultra -gate_clock -no_autoungroup -no_seq_output_inversion -no_boundary_optimization
..

And RTL code like following.
Module top
...
Input aclk;
Input i_hsync;

wire cg_clk;
assign cg_clk = i_hsync && aclk;

Block u_block(
.aclk (cg_clk),//(aclk)
...
...
);

wire cg_clk1;
assign cg_clk1 = i_hsync && aclk;

Block1 u_block1(
.aclk (cg_clk1),//(aclk)
...
...
);

There is no clock gated what i use cg_clk instead aclk.

Am i wrong use clock gating in rtl?
If i wrong please let me know how am i do?

 

[jbeniston]

-gate_clock inserts clock gating for logic in sequential processes (i.e. always @(posedge ...).

As you're specifying your own clock gating, it might not be necessary for DC to add any. We'd have to see all your logic.

BTW, don't gate the clock manually with:

cg_clk = i_hsync && aclk;

You should instantiate the clock gating cell, otherwise you may get glitches on the clock.

 

[u24c02]

Did you mean that i use clock gating cell instantiate instead using manually?
Did you means that Synthesizer find automatically clock gating?

but in the above example (for global clock gating), it's not gated. i don't know why not gated. is there any way method?

What am i do clock gating for global?

 

[layowblue]

One way to "direct" the synthesis tool for gated clock is to put enable signal on every sequential logic.
Like:
Flip-flops with an asynchronous reset and synchronous enable (good strategy for low power)

always_ff @(posedge clk or negedge rstb) 
 if ( rstb != 1'b1) begin 
 ... // Asynchronous set/reset actions 
 end 
 else begin 
 if (enable_condition==1'b1 ) begin 
 ... // Synchronous actions 
 end