markuswoltjer
Newbie level 5
Here I have the verilog for a simple clock divider, that brings a 2.03MHz clock down to a counter which counts at 1kHz... in other words once every millisecond.
I am using Lattice Diamond and going to run this on an FPGA as part of a bigger project but the error is blocking all of my progress.
Forgive me if it is an easy fix, this is my first week using Verilog or any HDL.
Here is the attempted synthesis:
Lastly, one may notice that the upper module in the hierarchy is a huge case statement called tekbotmoves. If need be, I can also post this code, but from what I can tell the problem is slow_count being driven by too many factors.
Thanks all!
I am using Lattice Diamond and going to run this on an FPGA as part of a bigger project but the error is blocking all of my progress.
Forgive me if it is an easy fix, this is my first week using Verilog or any HDL.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 module tekbotslide( input clk, output reg [17:0] slow_count); reg [10:0] fast_count; initial begin fast_count <= 0; slow_count <= 0; end always @ (posedge clk) begin fast_count <= fast_count + 1; if( fast_count > 2029) begin slow_count <= slow_count + 1; fast_count <= 0; end end endmodule
Here is the attempted synthesis:
Code:
Starting: "prj_run Synthesis -impl tekbotslide"
************************************************************
** Lattice Synthesis Engine **
************************************************************
synthesis -f "tekbotslide_tekbotslide_lattice.synproj"
synthesis: version Diamond (64-bit) 3.1.0.96
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.
Fri May 16 00:21:18 2014
Command Line: synthesis -f tekbotslide_tekbotslide_lattice.synproj -gui
-- all messages logged in file synthesis.log
Synthesis options:
The -a option is MachXO2.
The -s option is 4.
The -t option is TQFP144.
The -d option is LCMXO2-7000HE.
Using package TQFP144.
Using performance grade 4.
INFO:
INFO: ##########################################################
INFO: ### Lattice Family : MachXO2A
INFO: ### Device : LCMXO2-7000HE
INFO: ### Package : TQFP144
INFO: ### Speed : 4
INFO: ##########################################################
INFO:
Optimization goal = Balanced
Top-level module name = tekbotmoves.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true (default)
DSP utilization = 100 % (default)
fsm_encoding_style = auto
resolve_mixed_drivers = 0
INFO: fix_gated_clocks = 1
Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Use IO Insertion = TRUE
Use IO Reg = TRUE
Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/Users/Markus/Desktop (searchpath added)
-p C:/lscc/diamond/3.1_x64/ispfpga/xo2c00/data (searchpath added)
-p C:/Users/Markus/Desktop/tekbotslide (searchpath added)
-p C:/Users/Markus/Desktop (searchpath added)
Verilog design file = C:/Users/Markus/Desktop/tekbotslide.v
Verilog design file = C:/Users/Markus/Desktop/tekbotmoves.v
NGD file = tekbotslide_tekbotslide.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is OFF.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
-- Technology check ok...
Compile design.
Compile Design Begin
Top module name (Verilog): tekbotmoves
INFO - c:/users/markus/desktop/tekbotmoves.v(1): compiling module tekbotmoves. VERI-1018
INFO - c:/users/markus/desktop/tekbotmoves.v(57): compiling module tekbotslide. VERI-1018
Last elaborated design is tekbotmoves()
Loading NGL library 'C:/lscc/diamond/3.1_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.1_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.1_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.1_x64/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.1_x64/ispfpga.
Package Status: Final Version 1.36
Top-level module name = tekbotmoves.
GSR instance connected to net n1.
GSR will not be inferred because no asynchronous signal was found in the netlist.
WARNING - No .lpf file will be written because the -lpf option is not used or is set to zero.
INFO: Applying 200.000000 MHz constraint to all clocks
Results of NGD DRC are available in tekbotmoves_drc.log.
Loading NGL library 'C:/lscc/diamond/3.1_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.1_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.1_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.1_x64/ispfpga/or5g00/data/orc5glib.ngl'...
Running DRC...
ERROR - logical net 'slow_count_c_17' has multiple drivers
tekbotslide_1/slow_count_92__i17/REG/Q (L381) NON_PRIM OUT
slow_count_pad_17/IOBUF/O (L610) NON_PRIM OUT
ERROR - logical net 'slow_count_c_16' has multiple drivers
tekbotslide_1/slow_count_92__i16/REG/Q (L382) NON_PRIM OUT
slow_count_pad_16/IOBUF/O (L611) NON_PRIM OUT
ERROR - logical net 'slow_count_c_15' has multiple drivers
tekbotslide_1/slow_count_92__i15/REG/Q (L383) NON_PRIM OUT
slow_count_pad_15/IOBUF/O (L612) NON_PRIM OUT
ERROR - logical net 'slow_count_c_14' has multiple drivers
tekbotslide_1/slow_count_92__i14/REG/Q (L384) NON_PRIM OUT
slow_count_pad_14/IOBUF/O (L613) NON_PRIM OUT
ERROR - logical net 'slow_count_c_13' has multiple drivers
tekbotslide_1/slow_count_92__i13/REG/Q (L385) NON_PRIM OUT
slow_count_pad_13/IOBUF/O (L614) NON_PRIM OUT
ERROR - logical net 'slow_count_c_12' has multiple drivers
tekbotslide_1/slow_count_92__i12/REG/Q (L386) NON_PRIM OUT
slow_count_pad_12/IOBUF/O (L615) NON_PRIM OUT
ERROR - logical net 'slow_count_c_11' has multiple drivers
slow_count_92__i11/REG/Q (L602) NON_PRIM OUT
slow_count_pad_11/IOBUF/O (L616) NON_PRIM OUT
ERROR - logical net 'slow_count_c_10' has multiple drivers
tekbotslide_1/slow_count_92__i10/REG/Q (L387) NON_PRIM OUT
slow_count_pad_10/IOBUF/O (L617) NON_PRIM OUT
ERROR - logical net 'slow_count_c_9' has multiple drivers
tekbotslide_1/slow_count_92__i9/REG/Q (L388) NON_PRIM OUT
slow_count_pad_9/IOBUF/O (L618) NON_PRIM OUT
ERROR - logical net 'slow_count_c_8' has multiple drivers
tekbotslide_1/slow_count_92__i8/REG/Q (L389) NON_PRIM OUT
slow_count_pad_8/IOBUF/O (L619) NON_PRIM OUT
ERROR - logical net 'slow_count_c_7' has multiple drivers
tekbotslide_1/slow_count_92__i7/REG/Q (L390) NON_PRIM OUT
slow_count_pad_7/IOBUF/O (L620) NON_PRIM OUT
ERROR - logical net 'slow_count_c_6' has multiple drivers
tekbotslide_1/slow_count_92__i6/REG/Q (L391) NON_PRIM OUT
slow_count_pad_6/IOBUF/O (L621) NON_PRIM OUT
ERROR - logical net 'slow_count_c_5' has multiple drivers
tekbotslide_1/slow_count_92__i5/REG/Q (L392) NON_PRIM OUT
slow_count_pad_5/IOBUF/O (L622) NON_PRIM OUT
ERROR - logical net 'slow_count_c_4' has multiple drivers
tekbotslide_1/slow_count_92__i4/REG/Q (L393) NON_PRIM OUT
slow_count_pad_4/IOBUF/O (L623) NON_PRIM OUT
ERROR - logical net 'slow_count_c_3' has multiple drivers
tekbotslide_1/slow_count_92__i3/REG/Q (L394) NON_PRIM OUT
slow_count_pad_3/IOBUF/O (L624) NON_PRIM OUT
ERROR - logical net 'slow_count_c_2' has multiple drivers
tekbotslide_1/slow_count_92__i2/REG/Q (L395) NON_PRIM OUT
slow_count_pad_2/IOBUF/O (L625) NON_PRIM OUT
ERROR - logical net 'slow_count_c_1' has multiple drivers
tekbotslide_1/slow_count_92__i1/REG/Q (L396) NON_PRIM OUT
slow_count_pad_1/IOBUF/O (L626) NON_PRIM OUT
ERROR - logical net 'slow_count_c_0' has multiple drivers
tekbotslide_1/slow_count_92__i0/REG/Q (L352) NON_PRIM OUT
slow_count_pad_0/IOBUF/O (L627) NON_PRIM OUT
WARNING - logical net 'tekbotslide_1/fast_count_91_add_4_1/S0' has no load
WARNING - logical net 'tekbotslide_1/slow_count_92_add_4_19/CO' has no load
WARNING - logical net 'tekbotslide_1/slow_count_92_add_4_19/S1' has no load
WARNING - logical net 'tekbotslide_1/slow_count_92_add_4_1/S0' has no load
WARNING - logical net 'tekbotslide_1/fast_count_91_add_4_11/CO' has no load
ERROR - DRC failed with 18 errors and 5 warnings
Design Results:
350 blocks expanded
ERROR - NGD expansion failed.
Done: error code 2
Lastly, one may notice that the upper module in the hierarchy is a huge case statement called tekbotmoves. If need be, I can also post this code, but from what I can tell the problem is slow_count being driven by too many factors.
Thanks all!
Last edited by a moderator: