configuring FPGA using ethernet

[njsth]

i would like to know about configuring xilinx virtex-6 FPGA over ethernet under slave serial mode. i'm using lantronix's xport device and coolrunner CPLD. i am getting the serial data of the configuration binary file onto the cpld through xport now. i need to latch this data out to FPGA at cclk frequency without storing.

could anyone help me with the data latching and configuration clock frequency issue?

 

[ads-ee]

You know Ethernet has no requirement for guaranteed transmission of packets without some sort of upper layer protocol. Hence why there is TCP/IP, which can perform retransmission of packets.

Are you planning on keeping a fail safe fall back image in a serial flash device and the Ethernet is the flash update methodology? If you are planning on using the Ethernet directly you're going to have to buffer. Besides the issues with guaranteed transmission of packets you'll also have to deal with the IPG and the stripping the headers from the packets. I suppose you could stop the CCLK while you strip headers and during the IPG, but I think there is a lower limit to the CCLK frequency.

Regards

 

[FvM]

Slave serial mode is a synchronous, SPI-like protocol which isn't supported by a basic XPort. XPort AR can probably do it. Or some other protocol translation between XPort UART and configuration interface.

 

[njsth]

You know Ethernet has no requirement for guaranteed transmission of packets without some sort of upper layer protocol. Hence why there is TCP/IP, which can perform retransmission of packets.

Are you planning on keeping a fail safe fall back image in a serial flash device and the Ethernet is the flash update methodology? If you are planning on using the Ethernet directly you're going to have to buffer. Besides the issues with guaranteed transmission of packets you'll also have to deal with the IPG and the stripping the headers from the packets. I suppose you could stop the CCLK while you strip headers and during the IPG, but I think there is a lower limit to the CCLK frequency.

thank you for that immediate response.

yes, i'm using TCP/IP protocol and transferring the configuration file over a socket. at the other end i get chunks of 8 bits wrapped with start and stop bits. and no! i cannot store them on the receiving site. Rather i am told that i have to transfer the serial data directly for FPGA configuration at the clock frequency which FPGA expects.

Is there a way to do this?

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Or some other protocol translation between XPort UART and configuration interface.

thank you for your immediate response.

could you please brief me on the above statement?

 

[FvM]

I was primarly thinking of a small microcontroller.

 

[njsth]

okay. but i need to use a CPLD

 

[FvM]

CPLD should work, too. But it needs a sufficient number of logic cells and a clock to operate an UART receiver.

 

[ads-ee]

Scanning UG360, you can run the configuration in SelectMAP mode and in that case you can pause configuration by halting the CCLK or by controlling CSI_B (see pages 41 & 42. I didn't see anything about doing the same with Slave Serial configuration.

 

[njsth]

thank you all for your response.

i read that the non continuous clock is applicable for the slave serial mode also. but the problem is that it introduces delay in configuration and the bin file size is 9.3mb.
is there any other alternative? storing of large amount of serial data is not encouraged either.

 

[ads-ee]

I was suggesting that you use SelectMAP mode unless you can't afford the extra pins on the FPGA to implement that configuration scheme. It will allow you to both pause the configuration either with the CCLK or the CSI_B pin. The CPLD you are planning on using can perform serial to parallel conversion of the data and generate the control signals and CCLK.

 

[FvM]

I agree that parallel (SelectMAP) configuration interface will allow higher speed. But in the present case, the speed limitation is set by the ethernet serial interface. Even at the highest UART rate, data can be forwarded to the serial slave interface without additional delay.

To get an idea of achievable speed, you can simply drop the configuration data over your ethernet connection.

 

[ads-ee]

Wasn't considering higher speed. Just an easy way to gain extra time (clock cycles) to strip off the start/stop bits generate any control signals plus the CCLK and write the data to the configuration interface before the next byte shows up.

 

[FvM]

XPort supports up to 920 kBaud data rate. You can run the CPLD at 12 or 24 MHz and implement an UART receiver with odd oversampling ratio, e.g. 13. You have "all the time in the world" (at least 130 clock cycles) to shift each received byte into the FPGA.

 

[njsth]

Yes I understood the oversampling part.

I am not clear as to how the over sampled data is to be latched out at around 12MHz without modifying the configuration data(won't same bits be repeated while shifting out? )

 

[FvM]

I wrongly took the operation of an UART receiver as known technicque. You should be able to find HDL descriptions that can be adapted for your purpose and compiled to a CPLD.

You won't store more than one data byte during UART to serial slave protocol translation, or you can even pass single bits. CCLK is fully static and can be stopped and resumed at will.

You'll probably need a kind of control framing to mark begin and end of the configuration download. And you rely on data integrity guaranted by the ethernet layer.