String to STD_LOGIC_VECTOR converstion

[SharpWeapon]

String to STD_LOGIC_VECTOR conversion

Hi people,

I need some help. I have a text file which contains binary data(as shown below, the first row is 'a' and the second one is 'b' as for (a+bj)):
00000000 11110000
11110101 11110101
00010000 00000000
00001011 11110101
00000110 11110001
00010000 00000000

Then I read this file like this :
readData: out string(1 to 8);
dataRead: string(1 to 8);
--------------------
readline(toBeRead, inLine);
read(inLine, dataRead);
readData<=dataRead;

Now readData appears to be like this(Ex: for line 2 of the file):
'1','1','1', '1','0','1','0','1','HT','1','1','1','1','0','1','0','1'

But I want to read the file as STD_LOGIC_VECTOR(as 1111010111110101 Logic vector) not as string array.

What should I do? Or Is there a way to convert readData to one logic vector as I needed? Help is very much appreciated.


NB: I had tried to change the above code
readData: out STD_LOGIC_VECTOR(1 to 8);
dataRead: STD_LOGIC_VECTOR(1 to 8);
It has error, I think read() function can only operate on string types.

 

[TrickyDicky]

The easiest two options:
for older vhdl versions, you can include the following package:

use ieee.std_logic_textio.all;

and then read directly into a std_logic_vector.


or for vhdl 2008, you can do the same, but the above package is not needed as all textio functions are included in the std_logic_1164 library.

 

[ads-ee]

I suppose you could try this package.
https://www.mrc.uidaho.edu/mrc/people/jff/vhdl_info/txt_util.vhd

FYI. I found it in ~10 seconds using the following google search: "reading binary strings into std_logic_vector"


Tricky, thanks for that. I keep forgetting about all the packages that exist or the changes to the language that allow stuff that was in a package to now be done directly. This just one reason I dislike VHDL. The strong typing always derails my thought process when I'm trying to code my design. I've always got to go, now how do I convert this to something I can use over here.

 

[SharpWeapon]

Thank you all for the reply.
BTW, I have included textio.all package.

TrickyDicky, how can I read directly to STD_LOGIC_VECTOR, whenever I try to do that I have an error of 'expecting string' from read() function. Could you please edit the code i posted previously. BTW, I had also tried to make this conversion:
STD_LOGIC_VECTOR(to_unsigned(character'pos(dataRead(i)))) but this will just give me the ASCII of the characters in binary.

ads-ee, I just checked and tired this function from the package:

---

Code VHDL - [expand]
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function to_std_logic_vector(s: string) return std_logic_vector; 
 
readDataConv:   out STD_LOGIC_VECTOR(15 downto 0);
dataRead: string(1 to 16);
 
readline(toBeRead, inLine);
read(inLine, dataRead);     
readDataConv<=to_std_logic_vector(dataRead);

---

Then I have this error:

'current type string; expected type natural'.

 

[TrickyDicky]

you need to include ieee.std_logic_textio.all

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_textio.all;

use std.textio.all;

........

signal a : std_logic_vector(7 downto 0);

....

readline(f, l);
read(l, a);

--etc

- - - Updated - - -

and forget about dataRead and readData - you dont need a string.

- - - Updated - - -

btw, you really need to post the full code when you post. Your snippets are not very clear.

 

[SharpWeapon]

Thank you man! It worked. Sorry for not posting my full code, that was my first post.;-) Peace!