Hi,
I'm learning IC design and I'm bit confused about ring oscillator. I look at the "Wafer Acceptance Tests" data found on MOSIS website and it seems to me that they always use 31 stage to characterize the ring oscillator parameters. For example, in a TSMC 0.18um process, the MOSIS file shows this
Ring Oscillator Freq.
D1024_THK (31-stg,3.3V) 302.91 MHz
DIV1024 (31-stg,1.8V) 377.13 MHz
My questions are
1. What is special about 31 stage. I think ring oscillator can be any odd number of stages, right? Why must it be 31? Why can't it be 3, 5, 7, or 29, 33? Is there something special about 31 stage from a parameter extraction / characterization point-of-view?
2. What are the transistor ratio of the inverter MOSIS use to make their ring oscillator? Are they minimum-sized or they are something else?
This is my first post to this forum. I'm sorry if I don't put things in the right format. Please advise me. Thank you very much!
Best regards,
DG