Which of the == or === operator is synthesizable in verilog?

[snlaron]

which of the == or === operator is synthesizable in verilog?

 

[dave_59]

Re: verilog operator,which of the == or === operator is synthesizable in verilog?

Both. However you use === when you want to compare with X or Z, and that is not synthesizable.

 

[snlaron]

Re: verilog operator,which of the == or === operator is synthesizable in verilog?

Both. However you use === when you want to compare with X or Z, and that is not synthesizable.

Thank you sir. Since X or Z are not snythesizable , === is not snythesizable?

 

[dave_59]

Re: verilog operator,which of the == or === operator is synthesizable in verilog?

if (A === 0)

is functionally equivalent to

if (A == 0)

and both are synthesizable. However, some synthesis tools may choose not to support it.

 

[snlaron]

Re: verilog operator,which of the == or === operator is synthesizable in verilog?

Thank you again sir.
can you name some synthesis tools that can synthesize === operator?

 

[snlaron]

Re: verilog operator,which of the == or === operator is synthesizable in verilog?

if (A === 0)

is functionally equivalent to

if (A == 0)

and both are synthesizable. However, some synthesis tools may choose not to support it.

Thank you again sir.
can you name some synthesis tools that can synthesize === operator?