the difference of application and layout between isolation nmos and normal nmos ?

[mpig09]

Hi all:

There are two nmos models in the spice model : isolation nmos and normal nmos.
I simulate the i-v curve, and the result shows the curve are the same with isolation nmos and normal nmos.

Does anyone know the difference of application and layout between isolation nmos and normal nmos ?


Thanks for your view and reply.
mpig

 

[erikl]

In a standard CMOS process with p- substrate, the bulk of a normal nmos is automatically connected to the substrate: it is the substrate - which has the most negative potential of the circuit (GND). If an nmos is needed whose bulk should not be connected to GND, an isolated nmos is needed, whose bulk can be connected to some higher potential, e.g. to its source of a stacked nmos, by this eliminating the automatic positive source-to-bulk voltage which would change its threshold voltage and transconductance.

Again, in a standard CMOS process with p- substrate, such an isolated nmos has to reside in a separate pwell which is totally immersed in an nwell. For this, a twin well or triple well process is needed, s. e.g. this image:



So it's no surprise that the i-v-characteristics of both the normal and isolated nmos are identical if both have their sources connected to their bulks.

 

[mpig09]

Hi erikl:

Very thanks for your reply.
The reply let me more clear the iso-nmos.

I check the layout and re-simulate the gm and vth of iso-NMOS and nor-NMOS.

simulation:
The pic shows the simulation result:
N_ is a normal NMOS and vsb=0
N_iso is a iso-NMOS and sweep vsb=-1V ~ 0V




I hope erikl's reply and my simulation result will let us
to know iso-NMOS more clearly.

mpig