[SOLVED] Random number generation in SystemVerilog Test Bench

[BartlebyScrivener]

I am trying to create a new 5 bit number every rising clk edge in my test bench. I have written the following.

  always_ff@(posedge clk) begin
    if(~reset_n) begin
      i_request <= 0;
    end else begin
      i_request <= $dist_uniform(0, 0, 32);
    end
  end

But it only appears to create a random number once, and not on every clock edge.

What am I misunderstanding?

Many thanks.

 

[ads-ee]

You keep calling it with the seed of 0. Make the seed the last value returned.

Regards

 

[dave_59]

If you are already using SystemVerilog, use $urandom_range(32) which gives you better random stability than the Verilog $random and $dist_uniform calls. Every initial/always block gets an independent seed.

 

[mrflibble]

If you are already using SystemVerilog, use $urandom_range(32) which gives you better random stability than the Verilog $random and $dist_uniform calls. Every initial/always block gets an independent seed.

What do you mean with "better random stability"? Better distribution properties? Repeatability?

 

[dave_59]

Stability is the repeatability of a series of random numbers as you make changes to your testbench.

Suppose you had two always blocks generating random numbers. Then you make a change to the testbench so that the frequency of generating random numbers changes in one of the blocks. Maybe you get two random numbers or skip a random number in one cycle. If all the random number generators share the same seed variable, then the sequence of random numbers in the always block where you did not make a change will be affected. On the other hand, if you give each always block a separate seed variable, you need to make sure each variable begins with a different seed value, otherwise you may wind up with the same series of random values in each always block.

SystemVerilog takes care of this automatically by a specific algorithm that creates a seed variable for each thread as well as giving each variable a unique starting value.

 

[mrflibble]

SystemVerilog takes care of this automatically by a specific algorithm that creates a seed variable for each thread as well as giving each variable a unique starting value.

Thank you for the detailed explanation! Got it now. I guess the main new feature is a distinct seed for each seperate threads, which is indeed a good idea. I take it this is standardized behavior over all the simulators?

 

[dave_59]

See 18.14 Random stability in the 1800-2012 LRM

 

[mrflibble]

I can appreciate a pointed RTFM directive. Thanks. XD