So you tell me what kind of signal you are looking at that is: TTL or CMOS that has only on T1 on time/state and OFF time/state T2? You seem to think it's a common signal that everyone should know about. Well I don't know what signal it is, and given the fact that I'm the only one that has responded to this thread indicates to me that nobody else knows either. It bears repeating: A signal taken out of context is meaningless.
You seem to think because one (or a few) instances of signals you've looked at exhibit some specific behavior all signals are supposed to behave this way. A signal could potentially have a waveform with an extremely large variation in high/low pulse widths. Take for instance a 32-bit LFSR. Any single bit position picked will have a pseudo random sequence of 0's or 1's output from it, and I guarantee it won't look like your "common" (every other signal has to look like a T1-T2 pulse) signal.
I also don't understand what TTL or CMOS has anything to do with your T1, T2, T3, etc pulse widths observations. TTL and CMOS are logic families (i.e. the transistor circuit topology that makes a circuit behave like AND/OR/NOT/XOR etc logic gates) with a specific set of voltage level requirements. You could just as easily generate your "waveform" with BiCMOS, HSTL, SSTL, ECL, PECL, LVPECL, etc.
So explain what you mean by the logic family and pulse sequence not being normal or what logic family generates such a sequence. It's certainly not at all clear what your issue is with the signal (waveform) you drew.
I seriously wonder if you have any grasp on what digital logic is? Have you had any instruction or read any books on digital logic? Do you understand what logic families are? Do you understand what a scope shows you when it displays a signal? Do you understand logic levels 0/1, true/false, Boolean algebra? If what I'm saying doesn't make sense to you, then you need to do some studying of the basics first.
Regards