tjendon74
Junior Member level 3
I'm trying to implement (in VHDL) a simple 3-bit counter that is loaded asynchronously. The CPU writes to an 8-bit register, in which 3 of those bits are the ones that are loaded into the counter. These 3-bits determine the duty cycle for the PWM output that is gated on the TC of the counter.
Has anyone had any experience designing loadable counters in VHDL? Please let me know...
Thanks
tjendon74
Has anyone had any experience designing loadable counters in VHDL? Please let me know...
Thanks
tjendon74