what is the systhesis and timing models of a hard macro

[tybhsl]

what is the systhesis and timing models of a hard macro? How can I generate it for systhesis use later? Thanks

 

[floatgrass]

generally speaking, hard macro synthesis and timing model are from the third company.
or from the compiler, eg memory compiler.

 

[AlexWan]

Why to do synthesis on Hard-Macro? It is a GDSII, and is a IP for your design.

 

[videohu]

You can consider Hard-macro as verified black box.

 

[wadaye]

Hi tybhsl,

We need timing model in Synthesis because we need the hard block's timing info

for surronding blocks. We can get the timing_model from Primetime.

 

[mvvijay78]

Can anyone comment that is it allowed to do over the block routing for all the hard macros
Vicky

 

[wkc]

It depends. Some hard marcos are noise sensitive, e.g. specially tailored memory block, and you may not want any signal fly over it.

 

[tukken]

May be you should usr PT for hard block timing description

 

[haosg]

it is for convinence of chip level synthesis,
if IP provider don't provide the model, you can consider it as black box
and set timing constraint on boundary.

 

[tybhsl]

Thanks everyone!
One more question, if I want to synthesis a top Verilog file in which a hard macro IP is used as one of its submodules, how can I make the Eda tools---design compiler, to recognize this macro sucessfully although I can imagine it as a black box in my mind. Perhaps we need something like the standard cell library to tell the tool that this submodule should be treated as a blackbox. We call it the synthesis models of a hard macro. I mean, if I want design a hard macro for others, how can I generate such models so that others can synthesis it as a submodule? Thanks!

 

[tybhsl]

can you help me? I am puzzled at it for a long time. Thanks.

 

[jinruan]

generally speaking, hard ip provider will give you timing model, when use DC, you include your hard ip in link_library

 

[tybhsl]

But if am IP provider, how can I generate it for others?

 

[sxqzj]

it' s a good subject and useful to me
my question is how to generate the models
just like tybhsl asked!

 

[spauls]

Please clarify that your design is memory or IP.

 

[arm946es_softcore]

which tool can output analog block timing model?

 

[tybhs]

I have the some question as above. Who can help me? Thanks.

 

[qslazio]

use synopsys primetime and library compiler

 

[peen1]

I have heard that you can use synopsys to extract the timming information of an already exisiting macro.

As for creating the timming model I guess the synopsys library compiler should be useful.

 

[ken_ooi]

You can use ETM or ILM model.