Two clock domain- Problem!

[PeterUK2009]

Hi! I know this may sound very simple but pls stay with me!

I want to write my interface from the 0, so I get data parallel and want to sent it serial, well, I decided to do it with standard blocks so I used a shift register, I used block to divided to clock and the top for now is my control interface, I took the clock divided (Let called clock/38) on my main block very simple stuff I have a stage machine to control the interface an counter ticked by clock/38 to move a stage on the stage machine. All works but I have to make the load stage wait to clock stage on the clock/38 so you guess it now, if not let carry on.

All works but if I want to write constantly in the interface I get one clock/38 circle error.

The thing is my shifting block clock is fitted it with clock/38 I though it was going to be easy as you only need to count X number of clock and you are out. But it also need one clock as its a register to load the data in.

What is the best way to sort this out?

Is the solution to have two domain in the shift register? on to shift and one to load as signal in, and the use the signal "Write" to load into register?

Thanks,

 

[TrickyDicky]

How did you divide the clock? Logic? this could be a big problem. Much better to use a single clock domain and generate clock enables.

 

[K-J]

Hi! I know this may sound very simple but pls stay with me!

I want to write my interface from the 0, so I get data parallel and want to sent it serial, well, I decided to do it with standard blocks so I used a shift register, I used block to divided to clock and the top for now is my control interface, I took the clock divided (Let called clock/38) on my main block very simple stuff I have a stage machine to control the interface an counter ticked by clock/38 to move a stage on the stage machine. All works but I have to make the load stage wait to clock stage on the clock/38 so you guess it now, if not let carry on.

It's not clear to me what the state machine is clocked with, but I'll guess that it's clock/38

All works but if I want to write constantly in the interface I get one clock/38 circle error.

No idea what a 'circle error' is, but I'm guessing that when you write a lot that the design fails...which is the typical result when you use generated clocks inside an FPGA unless coming from a PLL or DLL

The thing is my shifting block clock is fitted it with clock/38 I though it was going to be easy as you only need to count X number of clock and you are out. But it also need one clock as its a register to load the data in.

I'm guessing that clock/38 in addition to being divided down from some higher frequency also comes to a stop and you need to be able to clock the register to load it.

What is the best way to sort this out?

The best way is to use one free running clock, not multiple clocks and not clocks generated within the device (assuming this is an FPGA).

Is the solution to have two domain in the shift register? on to shift and one to load as signal in, and the use the signal "Write" to load into register?

No, use just one clock along with a shift enable and a load enable signal like this...

process(clock)
   if rising_edge(clock) then
      if (load = '1') then -- assuming that 'load' takes precedence over 'shift'
         -- Load the register here
      elsif (shift = '1') then
         -- Shift the register here
      end if;
   end if;
end process;

You left out several very important points in your post that could affect the response since one has to make several assumptions:
- Is this to be implemented in a CPLD or FPGA? An ASIC?
- Why are you generating clock/38 in the first place? What's wrong with clock?
- What exactly is not working (i.e. what is a 'circle error')?
- Are there any signals generated from 'clock' that are then used by a process clocked by 'clock/38'?

Kevin Jennings

 

[PeterUK2009]

if rising_edge(clock) then
if (load = '1') then -- assuming that 'load' takes precedence over 'shift'
-- Load the register here
elsif (shift = '1') then
-- Shift the register here
end if;
end if;
end process;[/CODE]

Kevin Jennings

Hi I did try that this morning but load (one circle clock ) works but then slower clock as enable over lap and all shifting is over before even half circle of the clcok/38

So I did create another input to the clock call load and the evaluate:

  process(clk,reset,load,en)
   begin
      if (reset='1') then
         r_reg <= (others=>'0');
      elsif (clk'event and clk='1') then
		if (en'event and en='1') or (load='1') then
        r_reg <= r_next;
			end if;

load as = 1 evaluation is fine, but the evaluation (en'event and en='1') is not working I am sure bad HDL
if I put e=1 and you suggest and I tried I get all shifting at the speed of main clock. (I have verified this by simulating the code)

I was trying to count the number clock/38 on my main control, but is the solution to count here clock/38(with a counter) or to create at tick signal to fit in that even evaluation it would be easier is it could evaluate (en'event and en='1') so that would make works just fine, I think!

 

[TrickyDicky]

you cant do that - its like trying to detect a clock edge on a clock edge - and that never going to happen. You can only have 1 clock per process. Why not just create the enable like an enable (active once every 38 clocks).

 

[PeterUK2009]

you cant do that - its like trying to detect a clock edge on a clock edge - and that never going to happen. You can only have 1 clock per process. Why not just create the enable like an enable (active once every 38 clocks).

Because as I said before enable clock/38 is like a clock 19 main clock down 19 main clock up, to it keep shifting until 19 clocks at the speed of main clock! I guess I need to create a tick signal and fit it to this block! to tick using clock/38.

 

[TrickyDicky]

That post didnt make any sense to me.
You still havent justified why you need a clock/38? If its a straight division, a clock enable will almost always do the job.
Dont use clock/38 as an enable. Create a new signal, that is high for one clock and low for 37 clocks.

 

[mrflibble]

That post didnt make any sense to me.

...

Dont use clock/38 as an enable. Create a new signal, that is high for one clock and low for 37 clocks.

Precisely this.

 

[PeterUK2009]

process(clock)
   if rising_edge(clock) then
      if (load = '1') then -- assuming that 'load' takes precedence over 'shift'
         -- Load the register here
      elsif (shift = '1') then
         -- Shift the register here
      end if;
   end if;
end process;

Kevin Jennings

I used to this cote just because he is the only one pasting example code but I thanks all gave input and all read it and try.

I manage to do it now, I did that generate the clock/38 and create the ticks and then collected all up to the stage machine and now its seen to be working fine I have just evaluate 2 stages transmission it looks good a part from a glitch but I didnt that with purpose on my try to fix it the wrong way which I told it if its on standby or load or end transmission bring output to the 0 so it glitch when you send transmission constantly for 3 clock circle but I guess that is easy fix.

Before closing this post I would like to debate which way do you generate the clock/38 and the tick signal I didn't try to do it with counter but it got a bit messing so I did the easy way.

Also for example maybe following low power design should the interface clock turn off? would that be keeping the reset on which the interface is not in use? Maybe the other device would need the clock?

 

[TrickyDicky]

for a much better design, dont use clock/38 at all. It is very very poor design. Use clock enables instead.

 

[K-J]

Before closing this post I would like to debate which way do you generate the clock/38 and the tick signal I didn't try to do it with counter but it got a bit messing so I did the easy way.

signal Counter: natural range 0 to 37;
signal clk_div_38:  std_ulogic;
...
process(clock)
begin
   if rising_edge(clock) then
      if (reset = '1') or (Counter = 0) then
         Counter <= 37;
         clk_div_38 <= '1';
      else
         Counter <= Counter-1;
         clk_div_38 <= '0';
     end if;
   end if;
end process;

process(clock)
begin
   if rising_edge(clock) then
      if (clk_div_38 = '1') then
         -- Put whatever you have here that needs to be 'clocked' only by clock/38
      end if;
   end if;
end process;

Also for example maybe following low power design should the interface clock turn off?

You'll likely find that generating an internal clock will actually use more power. Try it for yourself though on a design, your design tools should have a power estimator function.

would that be keeping the reset on which the interface is not in use?

No idea what you're asking here

Maybe the other device would need the clock?

Then turning off the clock wouldn't be such a good idea

Kevin Jennings

 

[PeterUK2009]

process(clock)
begin
   if rising_edge(clock) then
      if (reset = '1') or (Counter = 0) then
         Counter <= 37;
         clk_div_38 <= '1';
      else
         Counter <= Counter-1;
         clk_div_38 <= '0';
     end if;
   end if;
end process;

process(clock)
begin
   if rising_edge(clock) then
      if (clk_div_38 = '1') then
         -- Put whatever you have here that needs to be 'clocked' only by clock/38
      end if;
   end if;
end process;

I can see one problem here right the way clock/38 is just a tick, two when I did it I try to do everything in one process. so It mean one counter (obliviously to create 38 counts), but I try to do the ticks with that counter evaluating with one process, it difficult because how you will need to evaluate when the could is 0000.. plus now the other tick is 76 but also you will have a delay from the process evaluating. I did try but it got messing and is was not evaluating right my IF net list.

your design tools should have a power estimator function.

Could you please give an example I cannot see what do you meant there

would that be keeping the reset on which the interface is not in use?
"RESET ON"*

My clock block already have clock, load, en, .... so adding another condition like power down, it mean modify the block again and the logic.

a simple resent <= '1' when reset = '1' and power down = '1' else '0'

Keep that block on reset mode, but would that do the trick?

Then turning off the clock wouldn't be such a good idea

I though about this because low power design ...bla...bla.... and I've looked at some code which turn the clock to 'Z' when its not used.

 

[PeterUK2009]

UPDATE:

I though it was done with this part but i guess it to fast I was trying to improve that delay/extra stage on the stage machine and I didnt some extra times simulations and I noticed that if which just before second clock is going high the fist bit shift is shorter it make send seen enable tick it will shift to the speed the clock, I though I fix it by making load to wait for a tick to get in sync but it would bit 1 but it give an error clock/38 when transmission is on constant. I thinking maybe I need to create a second load stage_machine? the machine was originally

standby-load-send_data-done_sending

I did a improvement from the first one if I have write High go to load , skip standby. this reduce one clock but still have 3 clock delays.

so there is two questions if you got lost, one do I need to create a sinc process , two do I need to evaluate what to do in last fit on Send_data? to not get any delays. Thanks

 

[TrickyDicky]

I get the feeling - whatever we tell you, you'll ignore the advice anyway, so why bother?

 

[K-J]

process(clock)
begin
   if rising_edge(clock) then
      if (reset = '1') or (Counter = 0) then
         Counter <= 37;
         clk_div_38 <= '1';
      else
         Counter <= Counter-1;
         clk_div_38 <= '0';
     end if;
   end if;
end process;

process(clock)
begin
   if rising_edge(clock) then
      if (clk_div_38 = '1') then
         -- Put whatever you have here that needs to be 'clocked' only by clock/38
      end if;
   end if;
end process;

I can see one problem here right the way clock/38 is just a tick

What problem do you think you see with having a one tick clock enable that goes off once for every 38 clocks? Most likely there is none, but since you seem to be focused on creating a clock (which you don't) you're completely missing the point of how to do a proper design in an FPGA/CPLD environment.

two when I did it I try to do everything in one process.

Then you just didn't do everything in one process correctly which means you didn't copy and paste correctly. In the example I gave, one would need to only copy and paste the section from 'if (clk_div_38 = '1') then...end if' into the first process and all would work exactly the same. If you didn't get the same result, then you didn't copy/paste correctly...I can't help you much on that front.

so It mean one counter (obliviously to create 38 counts), but I try to do the ticks with that counter evaluating with one process, it difficult because how you will need to evaluate when the could is 0000.. plus now the other tick is 76 but also you will have a delay from the process evaluating. I did try but it got messing and is was not evaluating right my IF net list.

All I can gather from this is that you did something and you found that it was difficult and didn't work. If you are trying to convey something else it isn't getting through.

Could you please give an example I cannot see what do you meant there

I have given you examples.

My clock block already have clock, load, en, .... so adding another condition like power down, it mean modify the block again and the logic.
a simple resent <= '1' when reset = '1' and power down = '1' else '0'
Keep that block on reset mode, but would that do the trick?

I suppose that means something to you, but not to anyone else.

I though about this because low power design ...bla...bla.... and I've looked at some code which turn the clock to 'Z' when its not used.

Ditto.

Since you've posted several times and not really been able to communicate just what you're doing and where exactly you're having trouble, I'd suggest that you instead post some real code (and testbench) and then just exactly what it is that you see that is wrong (i.e. signal xyz is 1 at time t=150 ns right after signal abc does ...).

Nebulous descriptions are getting nowhere. People here are willing to help, but you have the code and the knowledge of what you are trying to do...we do not

Kevin Jennings

 

[mrflibble]

How about you post a precise description of the specs, together with your latest complete code (lets pre-empt useless code snippets without context right now ) and testbench code AND a screenshot of that testbench AND your description of what is wrong with the signals in the testbench.

Without the above this thread is going nowhere... All I got from it so far is that part of the design has to run on a lower frequency than the rest for power saving reasons, and that's about it.

Oh, and while writing the description ... please pretend we have read what you wrote already and were unable to decipher what you meant. So try to reformulate, not regurgitate.

 

[PeterUK2009]

I get the feeling - whatever we tell you, you'll ignore the advice anyway, so why bother?

I guess you are feeling it wrong! I did it as It was suggested but if you do an enable (with the second clock domain) to do an syncro design you have sort part of the problem you still have two domains clocks.

I may be using the wrongs words or maybe none one has done a SPI from scratch. Its very simple in theory I have a code much more robust than the one I am doing and it was created in 2000 that mean 13 years so far.

Its very simple if you forget about control of the interface and work on the interface is down to counter, universal shift register, stage machine, do I need to write you the code?

 

[FvM]

I may be using the wrongs words or maybe none one has done a SPI from scratch. Its very simple in theory I have a code much more robust than the one I am doing and it was created in 2000 that mean 13 years so far.

The problem seems to be different. I guess all distributors to this thread have written SPI interfaces from the scratch many times and are aware of all kinds of problems that might arise on the way. But apparently nobody (me neither) understands what's your exact problem. That's why everybody asks for the code, a clear description or a testbench to shine a light on it.

 

[mrflibble]

I may be using the wrongs words or maybe none one has done a SPI from scratch. Its very simple in theory I have a code much more robust than the one I am doing and it was created in 2000 that mean 13 years so far.

Or maybe you should have used the word "SPI" sooner. This is the first time you have thrown in the SPI puzzle piece. My mind reading cap is at the cleaners and my regular voodoo doctor is vacationing in Egypt at the moment, so I am afraid we will have to make do with the written word.

So, how does SPI fit into the picture?

 

[PeterUK2009]

I have given you examples.

You said :

your design tools should have a power estimator function.

I am using ISE how do I estimate power on it?