28nm layout dependent effects query

Hello Friends,

Have some generic query on 28nm and lower technology nodes. Can someone point me to some reference material or explain the following layout dependent effects which are supposed to be more critical in lower technology nodes :

1. LOD
2. OSE ( OD spacing effect )
3. PSE ( Poly spacing effect )

How are these checked in DRC and what are the fix recommended ?

Need some urgent guidance on these.

Thanks

I can't give you any reference, the process documents should be your reference (other than layout textbooks), but maybe I can help you with how extraction works.

First of all, DRC doesn't care about layout dependent effects. It just checks that if everything is allright according to the rules defined in documents. So it doesn't care about what you put there, it doesn't care about how you put there, as long as you follow the DRC rules you can fabricate a Frankenstein of a circuit, maybe even some artistic work.

So LVS does care about what you put in that circuit and how you connected them. After that, the extraction tools are what you should really look into. So, after you get some circuit running, extraction determines the parameters that is going to be used in models for simulation, including the layout dependent effects. Actually you can see most of the parameters sent to the simulator by reading the netlist and/or models.

At last, to answer your real question: Basically there is no fix. The effects are always there, minimized by the process engineers. As a designer, you can isolate the ones that are special to you, but it is going to increase the area. For analog design, matching performance is also important, so same good practices apply, use dummies, read a lot of documents, gain experience, ???, profit.

I'm sorry for the vague answer.