What's VHDL equivalent to Verilog "Initial" block

[andy1]

vhdl initial

In Verilog, you use "Initial" block to initialize values. What would be VHDL equivalent? How do you initialize values on time in VHDL?

 

[nand_gates]

initial vhdl

In VHDL we use process statement in following way to mimic Verilog Initial block!

process
begin
   signal_a <= '0';
   signal_b <= "000000";
   .........
   .........
   .........
  wait;
end process;

Note here the last statement here must be a "wait"

One more thing to note here that in VHDL at signals declaration
you can assign initial values.
Hope this helps!

 

[masai_mara]

verilog initial

While the above is a neat solution, you can also use the now constructinside a process like :
if (now < 1ps) then
---
--
end if

 

[jitendra]

vhdl initial values

Hi,
There are 2-3 ways to achieve the similar results:
1.
Process statement without sensitivity list and a wait (only wait; not wait on/for etc.) statement as last statement in process.
Process statement will execute once and will be suspended on wait statement. Hence wait statement should be the last statement of process.

2. Give initial values to signals while declaration. In example below signal flag_sig will be initialized to '0'.

SIGNAL flag_sig : STD_LOGIC := '0';

Problem with this method is that initial values are generally not supported by synthesis tools, so the design behavior in actual hardware may not match with simulation results.

3. This is the best way to achieve the goal. You can say almost all the devices require Power-On Reset. As reset should be there in your design, you can specify reset values for all signals in your design. On power up, reset should be applied to chip as a result initial values are assigned to the corresponding signals.

Regards,
JItendra

 

[mhmhmh]

vhdl initial

Hi andy1

Take a look at application note from Xilinx: "Writing Efficient Testbenches"
https://www.xilinx.com/bvdocs/appnotes/xapp199.pdf

In this doc you can find info about differences in Verilog and VHDL in case of writing testbenches. All examples are in Verilog and VHDL. This should help you understand VHDL testbenches very quickly.

Cheers

 

[sarath51]

vhdl initial block

A process block with a wait statement in the end is the best replacement for the inital block

 

[smith_kang]

vhdl initial begin

hi
you can mimic Initial block in VHDL by Process(without sensitivity list),by giving Initial value to the signal in declaration of signal and by wait statement.