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sti effect and LOD effect

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STI, to first part, is a technological measure, needing several process steps. Its main effect is isolation and capacitance limitation.
But what is LOD? Do you perhaps think of LDD?

For both, you can find explanations in Wikipedia or G00GLE.
 

STI, to first part, is a technological measure, needing several process steps. Its main effect is isolation and capacitance limitation.
But what is LOD? Do you perhaps think of LDD?

For both, you can find explanations in Wikipedia or G00GLE.
Thanks erikl for the reply, STI - Shallow Trench Isolation, LOD -Length Of Diffusion, I have seen in some PDKs STI effect and LOD effect.
 

Hi all,

STI- Shallow Trench Isolation
LOD- Length of Diffusion

LOD:
The trenches do mechanical stress on the MOS causing change in the MOS behavior according to how far it is from the trench, so using dummy fingers decrease this effect cause you put the fingers far from the trench while using multipliers is better because all the MOS will have the same stress (better matched).

They are not exactly same, But most refer them with same name.

Since because of Shrinking Technology node, the spacing becomes very compact.
We use STI instead of LOCOS in smaller Tech, Due to STI used the source or drain will get the stress from STI and thus the operation point varies.

In order to avoid LOD, dummy transistors are placed and shared with critical devices, so that the stress is not reached to critical devices.


Attached is very good article on LOD and WPE:

Hope this helps!!
 

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  • WPE_LOD_Paper.pdf
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  • Matching_Of_Transistors.pdf
    61.2 KB · Views: 455

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