Need definitive answer: do SPICE PS/PD include the diffusion-gate boundary?

[quantized]

I'm finding a LOT of conflicting indications on how to calculate the PS and PD parameters for SPICE FETs. Nominally PD is the "perimeter of the drain". For a simple one-finger transistor that isn't butted up against another transistor, the drain is a rectangular region of diffusion; in one direction its size (let's call this the width) is dictated by the width of the transistor and in the other direction its length is dictated by the design rules (usually some sort of minimum diffusion-overhang-gate-by-X or diffusion-surrounds-contact-by-X rule).

If this diffusion region is W units wide and L units long, is this modeled by PD=2*W+2*L or PD=W+2*L?

The official **broken link removed** is very vague, simply saying "PD and PS are the perimeters of the drain and source junctions, in meters."

In Ken Martin's book there is a footnote on page 52 that very explicitly says "the perimiter does not include the edge between the junction and the active channel". This is in the chapter on SPICE. There's also an example on the following page that computes PS+PD using only three sides of the diffusion region.

The HSPICE MOSFET Models Manual is also obnoxiously vague, but an example on page 52 says "If you do not specify PD, then PDeff = M ⋅ (4 ⋅ HDIFeff + 2 ⋅ Weff)"; the use of (2 ⋅ Weff) rather than just Weff is clearly counting the gate edge of the transistor -- all four sides.

**broken link removed** says "If PS is not specified, then, For GEO=0 or 1, PSeff = 4*HDIFeff+Weff" implying that only three sides of the source are used.

What a mess.

Help! I don't just need an answer, I need to be sure it's the right answer. It's pretty crazy that this isn't clearly specified everywhere it appears, because getting this wrong results in parasitic capacitances that are off by 2x -- that's a huge error; not something you sweep under the rug.

 

[keith1200rs]

Hopefully someone will come along with a "definitive answer" if there is one, but it may be useful to know which models you are using? For example, in BSIM4.6.1 there is a PERMOD selector which defines "... whether PS/PD (when given) includes the gate-edge perimeter". In BSIM3V3.3 I believe the perimeter is treated as all four sides.

Keith

- - - Updated - - -

p.s. I notice that HSPICE supports PERMOD in BSIM4 so whether you include the gate edge in the perimeter would depend on the value of PERMOD in the models you have.

 

[quantized]

Hi Keith, thanks for taking the time to reply.

it may be useful to know which models you are using?

The model is Level 53 BSIM3 Version 3

For example, in BSIM4.6.1 there is a PERMOD selector which defines "... whether PS/PD (when given) includes the gate-edge perimeter".

Yow, it gets worse! So now there are three possibilities: included, excluded, and user-selectable. Ugh.

In BSIM3V3.3 I believe the perimeter is treated as all four sides.

Thanks, but do you have a reference for that?

p.s. I notice that HSPICE supports PERMOD in BSIM4 so whether you include the gate edge in the perimeter would depend on the value of PERMOD in the models you have.

I'm using HSIM (which is not the same thing as HSPICE… it was originally written by a different company even though both products now belong to Synopsys). Unfortunately the HSIM manual has almost zero documentation about how it handles transistor models. *sigh*

I suppose I could cook up a test SPICE deck to see what the simulator is actually doing, which is ultimately the real question I need an answer to.

 

[prestonee]

I use an internal sim tool and modified foundry deck that does take into account striping impacts on parasitics.
however a previous company i worked at used the tsmc default cards without modification was bsim 3 then 4.
in that case it did not take into account really anything. I found that the deck models had the equations implemented but werent being passed the information and thus default values were used(i think the defaults were 0 in that instance).
you need to make sure you are able to pass the information from schematic symbol to model, and if possible extraction to model.
but just because the model supports it doesn't mean your simulator is using it.

its kind of like building your super gaming computer, just because you have the best top of the line graphics card you need to make sure the processor, and memory don't limit it.
-Pb

 

[erikl]

Hello quantized,
perhaps you might want to read this forum discussion.

BTW: You can always specify your preferred PD value for each single MOSFET. In this case it won't be (re)calculated by the simulator, at least (not) by (H)SPICE & SPECTRE.

 

[quantized]

you need to make sure you are able to pass the information from schematic symbol to model

Yes, of course. I already discovered that the foundry had set rsh=0 which results in nrs+nrd being ignored.

But this question relates to how the tool interprets the foundry data. The foundry models specify the sidewall capacitance (CJGDsomethingOrOther) per meter of perimiter; the schematic specifies the "perimeter" of the source. The SPICE simulator gets to decide how to calculate the total capacitance using these two numbers.