Detecting contention in verilog?

[mtwieg]

Hello, currently I'm in a mixed signal CMOS class, and I'm writing verilog for a mixed signal device we'll eventually be implementing in Cadence. But to start with, I've been using active HDL-6.3 (just what we had lying around) for behavioral modelling, and I've mostly got things working within that environment. But one thing that really bothers me is that Active HDL does not seem to detect contention when setting registers. If I intentionally create contention in the verilog, then the compiler throws no errors or warnings. When I do behavioral simulation, it seems like it just chooses one of the contenders as the valid output (always resolves to a valid signal level, no X state or anything). I haven't defined any signal strengths so far. But I do see that the contention causes the simulated outputs to change, so the issue is there.

So basically, when there are contentions, Active-HDL isn't telling me in any way. Searching their help files for 'contention' yields absolutely no results. There is some sparse info on signal strengths, but only in regards to gate primitives (which I'm not using).

Years ago I had used verilog in Quartus II for cyclone FPGAs, and I recall that Quartus would always notify me of contention issues (not sure if it was in the verilog compiler or in the synthesis or simulation tools....), and I want that functionality for this project. Is this a limitation of Active-HDL 6.3? Or is contention something that is normally only checked at the synthesis stage of the design? When we eventually move to Cadence for development, how will contention issues be handled?

Thanks in advance.