Should timing slack be + or - ?

[davyzhu]

I found the timing parameter named 'slack' in synthesis tools, and I use XST.

For example, Path from Clock ’sysclk’ rising to Clock ’sysclk’ rising : 7.523ns
(Slack: -7.523ns). Should the slack be + or - ?

And how to choose the clock to pin timing and pin to clock timing when the main clock period is determined?

And any reference for newbie is welcome

Davy

 

[seansscheng]

You want to have "positive" slack, which means that timing is met.

 

[zhangpengyu]

It must be positive,otherwise timing is violate

 

[zhangpengyu]

It must be positive,otherwise timing is violate,
the same in dc.

 

[logicdrag]

Chosing clock to pin timing or pin to clock timing is strongly depended on your design period.
before CTS, you should set those timing by dc command.
Post CTS, you can define clock as propagate clock.
Optimization of Syntheis will make your slack more positive.thanks.

 

[tukken]

timing slack should be posetive
and Pin to clk and clk to Pin timing should be determined by you library

 

[hahaguy2]

slack is positive means you MET your timing
slack is negative means its a VIOLATION