FPGA-based floating-point logarithm unit

[bachoo786]

Hello everyone, I am working on a project titled "FPGA-based floating-point logarithm unit.” I chose an architecture which I found on the net by the title “Efficient Floating Point Logarithm Unit for FPGA” link is: **broken link removed**

I was a little confused on what library package should I use when computing (exponent.log2). Is there any standard library that would allow me to compute the first operand i.e. exponent.log2?

Also I had problems writing the vhdl code for the second operand i.e. log mantissa due to the use of a LUT. Can anyone please suggest?

Many thanks.

 

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Have you figured this out yet? I'm surprised no one has responded...

Well you can't just load a VHDL library to compute exponent.log2, besides if there was one it wouldn't be part of the IEEE standard libraries. ;-)


Anyway what your are trying to implement is described in the paper as:

log(num) = exp * log(2) + log(man)

where,
exp is the IEEE-754 exponent
man is the IEEE-754 mantissa
log(2) is a pre-computed constant

So to compute the exp * log(2) involves a multiplication function which you can use Coregen to produce a DSP48 implementation. Not sure how many bits they suggest for the log(2), but that will define how many bits you'll end up with in the result and the number of bits you'll have to deal with in the subsequent addition operation with the output of the log(man) table.

So the LUT they talk about is the log(man) lookup table to convert the mantissa to a log value which is a pretty big table so they used a quantized version of the table using some algorithm. If you want to use the full 32MB lookup table you'll have to create a mif file with your favorite scripting/programming language and produce the table. Generate a ROM in Coregen and specify the mif file. Now you have the look up table.

Hope this helps get your project going, looks like fun stuff.


Regards,
-alan

 

[bachoo786]

Have you figured this out yet? I'm surprised no one has responded...

Well you can't just load a VHDL library to compute exponent.log2, besides if there was one it wouldn't be part of the IEEE standard libraries. ;-)


Anyway what your are trying to implement is described in the paper as:

log(num) = exp * log(2) + log(man)

where,
exp is the IEEE-754 exponent
man is the IEEE-754 mantissa
log(2) is a pre-computed constant

So to compute the exp * log(2) involves a multiplication function which you can use Coregen to produce a DSP48 implementation. Not sure how many bits they suggest for the log(2), but that will define how many bits you'll end up with in the result and the number of bits you'll have to deal with in the subsequent addition operation with the output of the log(man) table.

So the LUT they talk about is the log(man) lookup table to convert the mantissa to a log value which is a pretty big table so they used a quantized version of the table using some algorithm. If you want to use the full 32MB lookup table you'll have to create a mif file with your favorite scripting/programming language and produce the table. Generate a ROM in Coregen and specify the mif file. Now you have the look up table.

Hope this helps get your project going, looks like fun stuff.


Regards,
-alan

Thanks for your reply Alan,

What do you suggest to calculate exp * log(2), a look up table or the Xilinx Floating point operator? the exponent here is 8 bits i.e. IEEE single precision. Therefore the number of combinations for the exponent when using the look up table would be 2^8 i.e. 256 different combinations multiplied by log 2, which is quite long.

For the second part i.e. log (man), I am not quite sure how to use the mif file and the 32mb lut. I am using Altium designer for my VHDL codes and simulation. Could you please explain how shall I go about that using Altium?

Many thanks.

Regards,

Ahmed

 

[mrflibble]

The best advice I can give you that goes for a lot of "floating point on fpga" projects:

step 1: reformulate your problem so it can be done with fixed point arithmetic
step 2: use lookup tables a lot
step 3: interpolate a lot
step 4: enjoy the peace of mind after escaping the floating point headache.

If you really really need floating point I'll shut up now.





PS: If you find some free IP for a good floating point unit out there solving your current problem, please post a link to it.

- - - Updated - - -

Generate a ROM in Coregen and specify the mif file. Now you have the look up table.

Or generate a vhdl/verilog file with the appropriate INIT statements, whichever is more convenient for you. As for scripting, I find that either a matlab/scilab script or a quick perl script usually does the trick. For something like this I'd probably do a matlab/scilab script.

 

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If one actually reads the paper referenced in the original message the algorithm used is not performing the log in floating point. The method is to perform a log operation without performing floating point math operations. Hence the restructuring of the problem into the equation I posted. That equation is being done with fixed point math. I'm not entirely sure of the positional offset of the add operation of the two addends though and I didn't notice if it was stated in the paper. Probably not as most of these types of research papers are notoriously vague when it comes to implementation details.

Personally I would use matlab/scilab to analyze the equation and determine how the numbers translate to the log and in that way you can also determine the number of bits you'll have to carry around to reach the requisite accuracy.

BTW, if I'm not being entirely clear...the result of the equation is not an IEEE-754 number.

To answer your questions:

What do you suggest to calculate exp * log(2), a look up table or the Xilinx Floating point operator?

This is a straight multiplication of two fixed point numbers as log(2) is a constant. The paper even suggests that you can perform the log with any base you want by changing the constant and the look-up table. So if you really wanted to make it a LUT then it's only 256 entries deep with a width that is determined by your resolution requirements.

For the second part i.e. log (man), I am not quite sure how to use the mif file and the 32mb lut. I am using Altium designer for my VHDL codes and simulation. Could you please explain how shall I go about that using Altium?

Sorry I don't know anything about Altium. What I was referring to is Xilinx's Core Generator tool, which is part of the ISE or Vivado suite. Considering the potential size of the file I suggested the mif as it's just a text file separate from the RTL of the design. mrfibble's right you could use INIT statements in your code but 32K of them?

Regards,
-alan

 

[bachoo786]

Well from what I was been told by my supervisor was that the paper is just to get an architecture and imply how the logarithm of floating point can be done in vhdl.

Like the paper shows when log is applied to the general format of a floating point number you end up with 2 operands which need to be added for the final answer i.e. (exp * log 2) and (log mantissa). The final answer will obviously be in binary.

The issue arises when log 2 comes in for the exponent, but again when a look up table is used, my supervisor told me I could calculate log 2 using a calculator, convert the answer to binary and than use it to multiply it with each 256 different combinations of the exponent (as Exp=8bits). From here there will be many outputs due to 256 different combinations.

My question is that how am I be able to add all of these 256 outputs to the second operand i.e. log mantissa? We need to remember that mantissa for single precision is 23 bits and that means there will be 2^23 different combinations if I am using a LUT and performing logarithm for each of 2^23 combinations. How on earth are all of these combinations of the exponent and mantissa added together? 8-O

Ahmed

 

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The issue arises when log 2 comes in for the exponent, but again when a look up table is used, my supervisor told me I could calculate log 2 using a calculator, convert the answer to binary and than use it to multiply it with each 256 different combinations of the exponent (as Exp=8bits). From here there will be many outputs due to 256 different combinations.

Huh? A constant multiplied with an 8-bit exp value is going to only have one output result for any given exp input. Do you even know what a look up table does?

My question is that how am I be able to add all of these 256 outputs to the second operand i.e. log mantissa?

What makes you think you add 256 values to the log of the mantissa? The multiplication is (constant * variable), which I think still has 1 result for any single variable value.

We need to remember that mantissa for single precision is 23 bits and that means there will be 2^23 different combinations if I am using a LUT and performing logarithm for each of 2^23 combinations. How on earth are all of these combinations of the exponent and mantissa added together? 8-O

Why don't you read the paper, they don't use the full 23 bit mantissa. Once again you WON'T have 256 outputs simultaneous you will have one output for the exp that came from the single IEEE-754 number you were converting. So you're calculation is an add of the result of exp*log(2) multiplication and the log conversion of mantissa (a.k.a. LOOK-UP TABLE).

You seem to think that the algorithm calculates all permutations of an IEEE-754 number simultaneously. If that is your intention then tell your supervisor you need to order an XC10V200000000FF2000-5 part and that the project can't be completed till around 2020, which is hopefully when technology catches up to the amount of logic you will need. ;-)

 

[bachoo786]

Right so I forgot to mention but I am new to VHDL and maybe that is why we are not on the same wavelength.

Fair to say what you explained me above but may I ask you one thing: after writing down the VHDL code for the LUT for (exp*log2) what’s the next step? as in how do you perform the addition with (log mantissa)? Could you write the VHDL code for the LUT?

Thanks!

 

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I'm getting the impression that you are really a SW type, that the MBA type (non-tech) assigned to the job because "VHDL looks like SW".

Well VHDL is not SW. It's HW pretending to be SW.

as in how do you perform the addition with (log mantissa)?

+

Could you write the VHDL code for the LUT?

Of course given enough incentive I could write the code for you...

As a consultant I charge $120/hr, but I will have to pass on the job as I'm too busy with my day job. Maybe you can find someone else to take the job...

 

[mrflibble]

You seem to think that the algorithm calculates all permutations of an IEEE-754 number simultaneously. If that is your intention then tell your supervisor you need to order an XC10V200000000FF2000-5 part and that the project can't be completed till around 2020, which is hopefully when technology catches up to the amount of logic you will need. ;-)

Oh oh oh! Can I preorder a few of those XC10V200000000FF2000's? 2^23 logic elements in parallel is going to be awesome! Do you also take orders for the accompanying small nuclear plant?