Shrinked technology nodes

[ivlsi]

Shrunk technology nodes

Hi All,

Why shrunk technology nodes are preferred over the regular one (e.g. 40nm vs 45nm)?

Why these nodes are called "shrunk nodes" and not just "new nodes"?

Thank you!

 

[rca]

Itis generally for ram process, to have more bit by area.

 

[ivlsi]

Could RAM/Memory be produced with one technology, but STD cells with another? As far as I understand, all of then are located on the same silicon layer...

 

[rca]

no, but the "standard" process like 0.13um are used all king of element ram/rom/std cell, and a shrink are made to 0.11um, to reduce area.
this shrink is more for very high volume component like ddram and I beleived "pure" digital.

 

[saurabhr8here]

The 40nm node for digital logic came into works when the pure-play foundries (TSMC, GLOBALFOUNDRIES, etc.) were not able to get their 45nm yields on time to compete with Intel. So they decided to skip 45nm, and move to a 'shrunk' or half-node, i.e. 40nm. Here the transistor dimensions and metal 1 dimensions scale at a slightly slower pace compared to a complete shrink or a new node (less than the regular 0.7X reduction). Hence, you'll find nearly all foundries other than Intel (which, of course, is an IDM) going to nodes called 40nm, 28nm, 20nm etc., while Intel is continuing its earlier scaling trend of 45nm, 32nm, 22nm and so on. Also note that some foundries like Samsung do offer 45nm and 32nm nodes. Performance wise you do see similar 'delta' from 40 to 28 as you see from 45 to 32. However, I am not sure how much improvement 40nm gives in comparison to 45 other than area benefits.

I am not really aware of memory technology (DRAM) scaling, however they do tend to scale at a faster pace compared to the microprocessor/SoC industry. Btw, standard cells and SRAM/Memory Compilers are built using the same process but the foundries supply the SRAM bitcell with scaled dimensions, i.e. they do not follow the regular DRC limited dimensions of logic devices/metals. This is to ensure maximum transistor density.

 

[ivlsi]

So, if someone tell me that a chip is produced in 45nm node, should I understand that ALL its elements (STD cells, Memories, I/Os, etc) are of the same technology of 45nm?

BTW, what does represent 45nm? Is this a length of the CMOS's tunnel (so called "length of transistor")?

Thank you!

 

[saurabhr8here]

Nowadays all foundries provide the option of 3 or more Vt transistors, very high Vt specialized transistors for SRAM and high voltage I/O devices. Also, you have multiple options for channel length, though these can be limited in very advanced nodes like 20nm. So you may design your chip using any combination of these to attain your goal of power/performance/area goals. But yes, all the components provided by the foundry will be of that technology node. That is because, the process flow is tuned and optimized for a specific node and it takes months, if not years to achieve that. Mixing nodes on a single chip is not a viable option.

Technology naming and convention follows the '1990s Moore's Law' tradition and today it is more of a marketing thing. Traditionally, a technology node represented the minimum printable feature (the gate length). So ideally the minimum gate length at 45nm node would be 45nm. This is also called the drawn length. However, the actual or effective channel length after fabrication used to be lower from 130nm down to 32nm due to S/D overlap and some foundries (Intel) would used aggresively scaled devices to speed up their node . However, beyond 45nm, scaling the actual transistor channel has become a huge challenge due to short-channel effects/high leakage and now the length is nearly stable at around 25nm. All all transistors from 45/32/28/22/20nm nodes will have a minimum 'effective' length of about 25nm. The node names still follow the traditional scaling convention of 0.7X reduction (32/45~0.7), but the gate length is not necessarily equal to the node name.

 

[ivlsi]

Also, you have multiple options for channel length

Does not the change in the transistor length mean a change in the technology node (e.g. from 45nm to 40nm)?

you may design your chip using any combination of these

Is it possible to mix different technologies in the same chip?

all the components provided by the foundry will be of that technology node

Hm... You wrote that transistors with different channel lengths might be used on the same chip... Does not that mean that they are from the different tech nodes? If the tech node doesn't represent the transistor's channel length, so what does it represent?

Doesn't transistors with different Vt mean transistors with different channel length?

 

[saurabhr8here]

Transistor length is not the only feature that is scaled when a technology is being scaled from one process node to another. The other notable changes include (but not limited to), channel doping, S/D doping, gate oxide scaling, poly-pitch and metal-pitch scaling. The fact that performance increases across technology nodes (earlier due to gate length scaling, but now due to strain engineering/HKMG, etc.) allows you to create smaller width transistors with similar or more drive current than the previous generation transistors.

Though changing the channel length will modify Vt, foundries supply multi-Vt transistors by changing the channel doping. So you'll have a Standard Vt, Low Vt and an Ultra-Low Vt transistor at 32nm with the same channel length. For more information on possible Vt/length combinations in a technology node check out papers published by Intel, TSMC and Samsung at IEDM. You may also check the ITRS roadmap. Also, when the foundries give multiple lengths, these are not necessarily the length of the previous generation. For example, in 32nm node, you can 'draw' (actual effective length will be smaller) channel lengths of 32nm, 36nm, 40nm (note that a 45nm channel length transistor in 32nm node will be better than the 45nm channel length transistor in 45nm process because of scaled oxide thickness, higher doping, etc.). However, you cannot draw a 40nm length transistor in a 45nm process. Again notice that I use the term 'draw' since the effective fabricated length will be different. Normally designers prefer to use the minimum size transistors for most part of their design because it gives them the best performance/power trade-off. Going for a longer length or high-Vt might be desirable to control leakage. But it depends on the design and application.

I will reiterate my point: The technode represents the minimum 'drawn' channel length of a transistor. However, the effective length has always been much lower till 32nm and it has been reversing around 28/20nm node (greater than the drawn length). The technology node also represents a bunch of other parameters such as oxide thickness, supply voltage (though that is scaled less aggresively now), channel doping, junction depth, poly and metal pitch. Check out a digital design textbook or the ITRS roadmap (www.itrs.net) for a detailed explanation.

 

[ivlsi]

smaller width transistors

How the transistor's width affect its performance? Does only transistor's resistance depends on the transistor's width?

channel length

Is channel length not a gate length? Are they the different things? Is it possible you draw a CMOS layout showing what is Gate Length and what is Transistor Length?

However, you cannot draw a 40nm length transistor in a 45nm process

Could it be said that the tech node number (45nm, 25nm, etc) just represents the smallest transistor's length in the given node?

As the CMOS smaller (has less length) as it faster and as it has more leakage? How does the transistor's width depends on its performance?

 

[saurabhr8here]

How the transistor's width affect its performance? Does only transistor's resistance depends on the transistor's width?

Yes, to the first order, the transistor's width only affects its resistance. Please note that in sub 100nm nodes, due to semiconductor manufacturing effects, transistors with different widths will behave differently (due to LOD: Length of Diffusion effects). But that is a different topic altogether. What I meant was, if you take a 45nm node transistor with minimum 'drawn' gate length (45nm) and W=100nm and then take a 32nm node transistor with drawn length=45nm and W=100nm, the 32nm would (or should), to the first order perform better because the rest of the parameters in the transistor are scaled, prominently gate oxide.

Is channel length not a gate length? Are they the different things? Is it possible you draw a CMOS layout showing what is Gate Length and what is Transistor Length?

I am sorry if I am confusing you with different terminologies. The channel length and transistor length are the same. That is the 'drawn' length or what you draw in a layout. But the effective length of the channel (Leff) is much smaller due to S/D overlap and other processing effects. Intel used to scale down the Leff to get improved performance as well. Hence the difference really is between 'drawn length' and 'effective length'. Remember that Leff is the real channel length that is finally manufactured. Leff is normally observed through TEM cross-section of the transistors and some SPICE models will give that value as well. Layout will only show the minimum allowable drawn length.

Could it be said that the tech node number (45nm, 25nm, etc) just represents the smallest transistor's length in the given node?

The tech node represents the minimum allowable 'drawn' length in the given node. The actual or Leff is different as I mentioned above. The technology node also gives you an idea of scaling because it has associated gate pitch/metal 1 pitch to it. For example, 28nm M1 pitch is 90nm and 20nm is 64nm (0.7X scaling). True 14nm M1 pitch should be 48nm. So the technology node does not just represent the transistor length, but a lot of other associated parameters as well. Also remember, that the technology naming is also a marketing gimmick. So even though Intel will say that it has moved from 32nm to 22nm node, the Leff remained at around 25nm for both nodes. But they still get performance improvement because of mobility enhancement by channel strain engineering. Conventional dimension (real channel length) scaling has reduced.

As the CMOS smaller (has less length) as it faster and as it has more leakage? How does the transistor's width depends on its performance?

I think I mentioned the effect of W on performance in answering the first question. To the first order, W only changes resistance. So increasing W will give you higher current, lower resistance. But in real manufacturing W has a lot of other second order effects.

I hope my answers are clearer now and I am not confusing you. In summary, please note that in the last decade (2002-2012) the actual channel length (Leff or physical length) has not scaled as aggresively as before and the technology node name are meant to represent a lot more parameters associated with the node, not just the minimum transistor length.

 

[ivlsi]

increasing W will give you higher current

So, in order to increase a driving strength of the cell, should I use wider transistors?

I hope my answers are clearer now and I am not confusing you

Your posts are REALLY useful! Thank you!

 

[saurabhr8here]

So, in order to increase a driving strength of the cell, should I use wider transistors?

Yes, you should increase the drive strength of the cell. However, please keep in mind that increase the width of the transistors (or gate size) increase its input capacitance or the load seen by the stage before it. The best way to size a series of gates would be to use Logical Effort. That should 'theoretically' give you minimum path delay.

Your posts are REALLY useful! Thank you!

You're welcome. I used this forum quite a lot as a student, so thought it would be a good idea to be more actively involved now.

 

[ivlsi]

Hm... In order to increase a strength of the cell, what transistors should be used - wider and shorter?

 

[saurabhr8here]

The short answer is that in order to increase the strength of a cell use wider transistors. But do keep in mind the implications of using larger cells. Current for a transistor in saturation is approximately equal to:

I ~ u*Cox*(W/L)(Vg-Vt)^alpha............where alpha is between 1 to 2 (used to be 2, or square law for long channel MOSFETs)

And for first order estimation delay is given by CV/I.

So you can increase I by increasing W, increasing your drive strength and reducing the delay of your cell. However, remember that the C in the delay equation is the load capacitance or the input capacitance to the next stage seen by your cell. Hence the load capacitance (to the first order) is Cload=Cox*W*L (Gate oxide capacitance*area of the gate). Hence, when you increase W, the load capacitance seen by the previous cell increases.

 

[ivlsi]

Waw! Really comprehensive response! In my guess you will contribute a lot to this forum!

 

[vlsi_int]

Hi Sir,
I know that this may not be relevant here but please tell me whether the unity gain frequency(Ft) of the transistor is dependant on the width of the transistor. For example if i have a graph plotted (90nm node) between Ft vs current density(Id/W) and i chose the maximum ft to design. Now if i change the width of the transistor by keeping the current density to be constant, does that mean my Ft is not changed. (I am not sure). Kindly help with this sir.