Leading zero anticipator

[Galos]

Hi,
Can anyone help me with the verilog code of leading zero anticipator. Its working seems a little tricky! Any sort of help will be appreciated... Thanks

 

[j_andr]

Hi,
Can anyone help me with the verilog code of leading zero anticipator.
Its working seems a little tricky!

google ?

not sure if the below is what you need, but it's tricky ... and quite fast;
in general - a '1' at position 'i' in input vector sets '1' at position
'i' in output vector and resets all output bits below 'i';

---

Code Verilog - [expand]
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module leading_zero
(
  input      [BIT_W-1:0] d_in,
  output reg [BIT_W-1:0] d_out,
  output reg [NR_W-1:0]  nr_of_zero,
  output reg [NR_W-1:0]  one_position
);
 
localparam BIT_W = 16,
           NR_W  = log2(BIT_W);
 
reg [BIT_W-1:0] clr;
genvar i;
 
generate
 for ( i=0; i<BIT_W-1; i=i+1)
  begin: CLR
    always @*  clr[i] <= |d_in[BIT_W-1:i+1];
  end
endgenerate
     
 always @* clr[BIT_W-1] <= !d_in[BIT_W-1];    
     
genvar x;
 
generate
  for (x=0; x<BIT_W; x=x+1)
    begin: lead_1
        ff_set_clr ff ( .set(d_in[x]),
                        .clr(clr[x]),
                        .q(d_out[x]) );
    end
endgenerate
 
integer y;
  always @*
    for ( y=0; y<BIT_W; y=y+1 )
      if      ( d_out == 0 ) nr_of_zero <= 0;
      else if ( d_out[y] )   nr_of_zero <= BIT_W-1 - y;
 
  always @*
    for ( y=0; y<BIT_W; y=y+1 )
      if      ( d_out == 0 ) one_position <= 0;
      else if ( d_out[y] )   one_position <= y + 1'b1;
 
/////////////////////////////////////////////////
function integer log2 ( input [31:0] value );   //
 begin  value = value-1;                        //
   for (log2 = 0; value > 0; log2 = log2+1)     //
           value = value >> 1;                  //
 end                                            //
 endfunction                                    //
/////////////////////////////////////////////////
    
endmodule
 
 
module ff_set_clr
(
  input      set, clr,
  output reg q
);
 
 always @(posedge set or posedge clr)
   if      ( clr )  q <= 1'b0;
   else if ( set )  q <= 1'b1;
   else             q <= q;
 
endmodule

---

j.a

 

[Galos]

Thanks for the quick reply! found it useful

 

[sainathreddy]

Thanks for the quick reply! found it useful

Did the code worked perfectly...? its an important block in my project so i can use it reply ASAP