Why ΣΔ converters have idle tones

[nickagian]

Hi guys,

although I have read lately several books and papers about ΣΔ ADCs, I still have not managed to get a clear answer to the question: Why do those ADCs have idle tones for DC or low amplitude tone inputs? Could someone explain me the mechanism behind this problem?

Moreover, as far as I have understood, this problem is more dominant for the 1st order 1-bit modulators and the higher the order or the resolution of the quantizer, the less obvious the idle tones are at the output. Is that true?

thanks a lot in advance,
Nikos

 

[Avla 0652]

Sorry, could you throw some light,
> "idle tones"
what do you mean?

 

[crutschow]

Let me Google that for you.

 

[saro_k_82]

Sigma delta converters employ feedback and compare present input against output to change the output and they have long memory. If the input is constant, the error keeps growing slowly and after a overflow the same scenario repeats. This causes same bit pattern to occur periodically, which means that the quantization noise would not be uniform and will favor a definite frequency (heavily colored) which is the inverse of pattern repetition rate. When the pattern becomes long (inputs close to quantization level) the tone falls at very low frequency where noise shaping fails to push it out of the band. If the input changes slightly rather than being constant, the pattern is destroyed and it helps to spread the quantization noise more evenly across the spectrum resulting in better SNR and therefore more bits out of the converter