marcelos
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Hi.
I'm working on a digital video evaluation project and trying to implement the evaluation process on a FPGA using VHDL.
The problem is: the equations that our project uses to rate the videos are a bit complex, with a lot of multiplications (of positive and negative numbers with decimal units) and also a exponential.
I try to simulate the code but the Quartus II compiler doesn't accept to compile a variable of the REAL type. And of course I can't work with just INTEGERs.
So the question (for now) is: how to use real/float/double numbers in a VHDL code and synthetize it? I've done some research and found some stuff about a library called ieee_proposed, but I have not been able to use it.
Thanks for any help.
I'm working on a digital video evaluation project and trying to implement the evaluation process on a FPGA using VHDL.
The problem is: the equations that our project uses to rate the videos are a bit complex, with a lot of multiplications (of positive and negative numbers with decimal units) and also a exponential.
I try to simulate the code but the Quartus II compiler doesn't accept to compile a variable of the REAL type. And of course I can't work with just INTEGERs.
So the question (for now) is: how to use real/float/double numbers in a VHDL code and synthetize it? I've done some research and found some stuff about a library called ieee_proposed, but I have not been able to use it.
Thanks for any help.