[STA] Should STA be run on Block Level?

[ivlsi]

Hi all,
Should STA be run on Block Level?
I just attended an interview and was told that STA should be run on the Chip Level only (and not in a Block Level). Is that true? Could someone give an example where STA must be run on the Block Level as well?
Thank you!

 

[yadavvlsi]

STA is first run at block level and then for top level. Before running top level STA block level reg2reg timing should be clean.

 

[ivlsi]

Is it not enough so that synthesizer check reg-to-reg paths during a logic synthesis? if it's not enough could you please explain why? Thank you

 

[yadavvlsi]

Synthesis uses wireload model for interconnect delay modelling but actual wire delay will be different depending on the placement of cells and routing. Also, clock skew comes in to picture in physical design while in synthesis clock is ideal. There are lot other factor like crosstalk, net resistance and capacitance etc will affect delays.

 

[ivlsi]

Okay, but the question was "Ever or Block-Level STA required?" in prior to physical implementation (prior to P&R and CTS).
As for Chip-Level STA, I guess it's required in prior to P&R and CTS, but what about a Block-Level STA?

 

[birdy123]

simple Ans is --- its require at block level also.

 

[ivlsi]

simple Ans is --- its require at block level also.

Could you give one-two scenarios why STA is required on the Block-Level?
What are the cases when the synthesizers miss some timing pitfalls, but STA discover them?
Why Timing Closure cannot be relayed just on the synthesis tools?

 

[dftrtl]

Its all about handling complexity.
If top level has many blocks then to easy the complexity better do STA at BLOCK level and use the .libs of those Block's for TOP level STA.

 

[ivlsi]

Thank you dftrtl! But how should sub-modules be characterized for input/output/max/min delays?
As far as I remember, *.lib files do not include timing information, but *.db do include... Should *.db files be used in STA instead of instead of *.lib?
Do *.db files include input/output delay information as well?
Should the sub-modules be replaced with *.db/*.lib instances in the Netlist level?
How interfaces between *.db/*.lib instances should be verified?
Thank you

 

[dftrtl]

.lib is meant to capture interface timing of BLOCK.
.db is synopsys native format (of .lib) which take less time to get processed by synopsys tool
In top level netlist Submodules definition should be removed
If you have generated .lib for BLOCK in a proper way, it takes care of timing when it is instantiated at TOP level.

 

[birdy123]

it will be good if you go through following links ...

Hierarchical Design Flow part1

Hierarchical Design Flow part2

above link let you know the importance of Block in the whole chip. Why it is required to close the block level timing also.

About the synthesis tool timing- see it all depends what all information is present at the time of synthesis. During synthesis - you don't have physical wires/metals- so no exact spef. So timing will not be accurate.
So in short why you can't relie on Synthesis tool - less accuracy because of less information.

I hope this will help you.

 

[ivlsi]

Thank you all!
It seems I asked my question in a wrong way...
The question is: is there a scenario ever STA & LEC is required for a Block on the Netlist BEFORE Place-&-Route? Let's say we just synthesized a Block (RTL-to-Gates). Is there a case we need to run STA and LEC on it before sending it to P&R?
Thank you!

 

[dftrtl]

For STA strategy we have answered you.
Coming to LEC every stage we run to see nothing is broken.