Circuit for Edge Detection of a digital signal

[abhaybonds]

Hi,
I want to design a self timed circuit in which two inputs affect the output. When input1 goes from 0 to 1, the output becomes 1 and when input 2 goes from 1 to 0, the output becomes 0. There is no change in the output for other transitions of the inputs.
It looks easy but I am not able to think of a suitable circuit.
I would be thankful if anybody could help me!!

Thank You

 

[sakthikumaran87]

Hi,

I dont know whether u are in need of a digital circuit or a HDL. I have attached the HDL code. You can even translate this to a circuit.

always@(posedge clk or negedge rst)
begin
if(~rst)
a_f <= 1'b0;
else
a_f <= input_a;
end
assign zero_to_one_transition = !a_f && input_a;
always@(posedge clk or negedge rst)
begin
if(~rst)
b_f <= 1'b0;
else
b_f <= input_b;
end
assign one_to_zero_transition = b_f && ! input_b;
always@(posedge clk 0r negedge rst)
begin
if(~rst)
output_f <= 1'b0;
else if(zero_to_one_transition)
output_f <= 1'b1;
else if(one_to_zero_transition)
output_f <= 1'b0;
end

endmodule

 

[abhaybonds]

Hi,
I wanted the circuit. I dont have any HDL software to convert it into circuit. Any other ideas?
Anyways thanks for the reply.

Thank you

 

[sakthikumaran87]

Hope it helps

- - - Updated - - -



Hope it helps

 

[abhaybonds]

Hi,
Thanks for giving circuits. But I was looking for a circuit without any external clock.
Anyways I figured it out. The idea lies in creating a short pulse from the inputs when they change levels and use these pulses to trigger a SR latch.
Thanks a lot for the help.

Thank You
Abhay