[SOLVED] Calculation of Clock speed of circuits based on delays

[elamparithi]

Hi all,

How the Clock speed calculated from the delays like Clk-to-Q delay and other delays???

 

[K-J]

Hi all,

How the Clock speed calculated from the delays like Clk-to-Q delay and other delays???

To first order...

Clock_period_minimum = Clock_to_Q_maximum - D_setup_to_Clock_maximum - Clock_Skew_maximum
Fmax = 1 / Clock_period_minimum

Kevin Jennings

 

[elamparithi]

Thanks KJ for the equation. What is called called clock skew maximum??

 

[K-J]

Thanks KJ for the equation. What is called called clock skew maximum??

Two devices that each receive a clock input from the same signal will not receive that signal at precisely the same time. The difference between the arrival time of the 'clock' signal at those two devices is called clock skew. Now if you consider a whole bunch of devices that each receive the 'same' clock signal, the arrival times of that signal at each of those devices can be different. Take the latest arrival time of the clock at a device and subtract the arrival time of the clock at the earliest device and you have the maximum clock skew for any of the devices that receive that clock signal.

Clock skew is added on when calculating the minimum clock period because effectively it is an uncertainty in the arrival time of the clock which is used to sample the data signals.

Depending on the context that you're asking your question, the clock skew might be measured in significant chunks of a nanosecond (say ~500 ps or less for a clock signal on a circuit board) or 10s of picoseconds or less for a clock signal inside a single device such as an FPGA.

Note: My equation in the earlier post subtracted out clock skew and setup time, rather than adding. The minimum clock period should be:

Clock_period_minimum = Clock_to_Q_maximum + D_setup_to_Clock_maximum + Clock_Skew_maximum

Basically it is saying that the minimum clock period is the sum of the following:
- The largest clock to output delay possible
- The largest data setup time relative to the clock that is possible
- The uncertainty in arrival times of the same nominal 'clock' between any two devices that communicate

Kevin Jennings