[SOLVED] DDR3 data length matching rules

[acm_45]

Hi,
I'm working for the first time with DDR3 ram components, I have to mount directly on the pcb 4 DDR3 modules controlled by a xilinx FPGA.
I'm a little bit confused by DDR3 layout rules, I understand that I've to follow the fly-by topology described in JEDEC specifications between the modules but my doubt is about the trace length matching from the fpga to the modules, in some specifications I read that all the data bus of all module must have the same length, in other documents I read that every module must have data bus as short as possible without a trace match between modules. Depending by these rules the pcb layout will result not so difficult or a nightmare.

I know that in the firmware I could delay the control signals but I want to design the best pcb layout.


Thank you in advance

 

[mishrashashi]

As per my experience with ddr3, the length matching is must. But tollarance of 2-5% is considerable good. Here is the datasheet (https://www.ti.com/lit/ds/symlink/tms320dm8148.pdf )which says impedance matching should be Z+ 5 Ohm. ( please refer section 8.13 in datasheet. In same data sheet, it is recommended to route the traces within maximum length. Thumb rules are essential to follow . But the requirement and the device specification can have tolarance at some extinct. hope for the best..


Hope this is useful to you

 

[acm_45]

Thank you for your answer!
I read the datasheet and in the bottom of page 320 there's a note that explain that length matching is required only within each byte lane, and each byte lane must match the strobe signal. That's what I was looking for.
Others signals Clock, address and control must match the trace length, right?

Thank you!
best regards

acm

 

[mishrashashi]

Other signals- Address and control signals should match in length according to DDR Clock signal.
For DDR3 routing, better to follow these steps.
1. Route clock signals
2. Address and control signals and
3. Data, Data mask and Data strobe Signals

 

[sivamani]

Match lengths byte lane wise ex 0-7,DM and DQS as a group .
Match Address group with Clock signal.
Not necessary to match Data group with respect to Address& Control and clock. And also data group to group .. In DDR3 there is a write leveling concept which will take care of delays between strobe and Clock..

- - - Updated - - -

Refer ug406.pdf for clear details..

 

[acm_45]

thank you for your answer,
after reading lots of documents I routed the DDR3, now is working fine at full speed!
Best regards