Newbie designed PCB crosstalk problem: 5MHz clk cross coupled to GND

[wandola]

I am a newbie. I designed a PCB without any supervision 'cause I have nobody to consult.

It is a 4-layer PCB to test a ADC chip. The PCB is shown below.

I found that my differential AC signals to the ADC input have been distorted. I think the clk signal is coupled to the the ground plane first. Then coupled to other part of the circuit.

Indeed, the power supply, the LDO output, and even ground plane are all distorted by a periodic signal which is in accordance with the clk.

Is there anything I can do to solve this problem? Or I have to redesign a new PCB...


Pls help the newbie...

 

[FvM]

Statement like below suggest, that you have in the first place a problem of probing your circuit correctly. I don't believe any of your measurements.

Indeed, the power supply, the LDO output, and even ground plane are all distorted by a periodic signal

Nevertheless there may be real clock-to-signal crosstalk. But the differential signalling should eliminate it in a first order for the ADC interface. If the said 5 MHz is the ADC clock, you would see the interference at worst as a DC offset.

 

[gongdori]

Out of curiosity, do you have one gnd plane for both digital and analog, or two split planes?
How do you generate clock signal (in what standard) and how they are distributed?
I'm not really an expert, but trying to understand why it happens...